// Code generated from _gen/*Ops.go using 'go generate'; DO NOT EDIT.

package ssa

import (
	"cmd/internal/obj"
	"cmd/internal/obj/arm"
	"cmd/internal/obj/arm64"
	"cmd/internal/obj/loong64"
	"cmd/internal/obj/mips"
	"cmd/internal/obj/ppc64"
	"cmd/internal/obj/riscv"
	"cmd/internal/obj/s390x"
	"cmd/internal/obj/wasm"
	"cmd/internal/obj/x86"
)

const (
	BlockInvalid BlockKind = iota

	Block386EQ
	Block386NE
	Block386LT
	Block386LE
	Block386GT
	Block386GE
	Block386OS
	Block386OC
	Block386ULT
	Block386ULE
	Block386UGT
	Block386UGE
	Block386EQF
	Block386NEF
	Block386ORD
	Block386NAN

	BlockAMD64EQ
	BlockAMD64NE
	BlockAMD64LT
	BlockAMD64LE
	BlockAMD64GT
	BlockAMD64GE
	BlockAMD64OS
	BlockAMD64OC
	BlockAMD64ULT
	BlockAMD64ULE
	BlockAMD64UGT
	BlockAMD64UGE
	BlockAMD64EQF
	BlockAMD64NEF
	BlockAMD64ORD
	BlockAMD64NAN
	BlockAMD64JUMPTABLE

	BlockARMEQ
	BlockARMNE
	BlockARMLT
	BlockARMLE
	BlockARMGT
	BlockARMGE
	BlockARMULT
	BlockARMULE
	BlockARMUGT
	BlockARMUGE
	BlockARMLTnoov
	BlockARMLEnoov
	BlockARMGTnoov
	BlockARMGEnoov

	BlockARM64EQ
	BlockARM64NE
	BlockARM64LT
	BlockARM64LE
	BlockARM64GT
	BlockARM64GE
	BlockARM64ULT
	BlockARM64ULE
	BlockARM64UGT
	BlockARM64UGE
	BlockARM64Z
	BlockARM64NZ
	BlockARM64ZW
	BlockARM64NZW
	BlockARM64TBZ
	BlockARM64TBNZ
	BlockARM64FLT
	BlockARM64FLE
	BlockARM64FGT
	BlockARM64FGE
	BlockARM64LTnoov
	BlockARM64LEnoov
	BlockARM64GTnoov
	BlockARM64GEnoov
	BlockARM64JUMPTABLE

	BlockLOONG64EQZ
	BlockLOONG64NEZ
	BlockLOONG64LTZ
	BlockLOONG64LEZ
	BlockLOONG64GTZ
	BlockLOONG64GEZ
	BlockLOONG64FPT
	BlockLOONG64FPF
	BlockLOONG64BEQ
	BlockLOONG64BNE
	BlockLOONG64BGE
	BlockLOONG64BLT
	BlockLOONG64BGEU
	BlockLOONG64BLTU
	BlockLOONG64JUMPTABLE

	BlockMIPSEQ
	BlockMIPSNE
	BlockMIPSLTZ
	BlockMIPSLEZ
	BlockMIPSGTZ
	BlockMIPSGEZ
	BlockMIPSFPT
	BlockMIPSFPF

	BlockMIPS64EQ
	BlockMIPS64NE
	BlockMIPS64LTZ
	BlockMIPS64LEZ
	BlockMIPS64GTZ
	BlockMIPS64GEZ
	BlockMIPS64FPT
	BlockMIPS64FPF

	BlockPPC64EQ
	BlockPPC64NE
	BlockPPC64LT
	BlockPPC64LE
	BlockPPC64GT
	BlockPPC64GE
	BlockPPC64FLT
	BlockPPC64FLE
	BlockPPC64FGT
	BlockPPC64FGE

	BlockRISCV64BEQ
	BlockRISCV64BNE
	BlockRISCV64BLT
	BlockRISCV64BGE
	BlockRISCV64BLTU
	BlockRISCV64BGEU
	BlockRISCV64BEQZ
	BlockRISCV64BNEZ
	BlockRISCV64BLEZ
	BlockRISCV64BGEZ
	BlockRISCV64BLTZ
	BlockRISCV64BGTZ

	BlockS390XBRC
	BlockS390XCRJ
	BlockS390XCGRJ
	BlockS390XCLRJ
	BlockS390XCLGRJ
	BlockS390XCIJ
	BlockS390XCGIJ
	BlockS390XCLIJ
	BlockS390XCLGIJ

	BlockPlain
	BlockIf
	BlockDefer
	BlockRet
	BlockRetJmp
	BlockExit
	BlockJumpTable
	BlockFirst
)

var blockString = [...]string{
	BlockInvalid: "BlockInvalid",

	Block386EQ:  "EQ",
	Block386NE:  "NE",
	Block386LT:  "LT",
	Block386LE:  "LE",
	Block386GT:  "GT",
	Block386GE:  "GE",
	Block386OS:  "OS",
	Block386OC:  "OC",
	Block386ULT: "ULT",
	Block386ULE: "ULE",
	Block386UGT: "UGT",
	Block386UGE: "UGE",
	Block386EQF: "EQF",
	Block386NEF: "NEF",
	Block386ORD: "ORD",
	Block386NAN: "NAN",

	BlockAMD64EQ:        "EQ",
	BlockAMD64NE:        "NE",
	BlockAMD64LT:        "LT",
	BlockAMD64LE:        "LE",
	BlockAMD64GT:        "GT",
	BlockAMD64GE:        "GE",
	BlockAMD64OS:        "OS",
	BlockAMD64OC:        "OC",
	BlockAMD64ULT:       "ULT",
	BlockAMD64ULE:       "ULE",
	BlockAMD64UGT:       "UGT",
	BlockAMD64UGE:       "UGE",
	BlockAMD64EQF:       "EQF",
	BlockAMD64NEF:       "NEF",
	BlockAMD64ORD:       "ORD",
	BlockAMD64NAN:       "NAN",
	BlockAMD64JUMPTABLE: "JUMPTABLE",

	BlockARMEQ:     "EQ",
	BlockARMNE:     "NE",
	BlockARMLT:     "LT",
	BlockARMLE:     "LE",
	BlockARMGT:     "GT",
	BlockARMGE:     "GE",
	BlockARMULT:    "ULT",
	BlockARMULE:    "ULE",
	BlockARMUGT:    "UGT",
	BlockARMUGE:    "UGE",
	BlockARMLTnoov: "LTnoov",
	BlockARMLEnoov: "LEnoov",
	BlockARMGTnoov: "GTnoov",
	BlockARMGEnoov: "GEnoov",

	BlockARM64EQ:        "EQ",
	BlockARM64NE:        "NE",
	BlockARM64LT:        "LT",
	BlockARM64LE:        "LE",
	BlockARM64GT:        "GT",
	BlockARM64GE:        "GE",
	BlockARM64ULT:       "ULT",
	BlockARM64ULE:       "ULE",
	BlockARM64UGT:       "UGT",
	BlockARM64UGE:       "UGE",
	BlockARM64Z:         "Z",
	BlockARM64NZ:        "NZ",
	BlockARM64ZW:        "ZW",
	BlockARM64NZW:       "NZW",
	BlockARM64TBZ:       "TBZ",
	BlockARM64TBNZ:      "TBNZ",
	BlockARM64FLT:       "FLT",
	BlockARM64FLE:       "FLE",
	BlockARM64FGT:       "FGT",
	BlockARM64FGE:       "FGE",
	BlockARM64LTnoov:    "LTnoov",
	BlockARM64LEnoov:    "LEnoov",
	BlockARM64GTnoov:    "GTnoov",
	BlockARM64GEnoov:    "GEnoov",
	BlockARM64JUMPTABLE: "JUMPTABLE",

	BlockLOONG64EQZ:       "EQZ",
	BlockLOONG64NEZ:       "NEZ",
	BlockLOONG64LTZ:       "LTZ",
	BlockLOONG64LEZ:       "LEZ",
	BlockLOONG64GTZ:       "GTZ",
	BlockLOONG64GEZ:       "GEZ",
	BlockLOONG64FPT:       "FPT",
	BlockLOONG64FPF:       "FPF",
	BlockLOONG64BEQ:       "BEQ",
	BlockLOONG64BNE:       "BNE",
	BlockLOONG64BGE:       "BGE",
	BlockLOONG64BLT:       "BLT",
	BlockLOONG64BGEU:      "BGEU",
	BlockLOONG64BLTU:      "BLTU",
	BlockLOONG64JUMPTABLE: "JUMPTABLE",

	BlockMIPSEQ:  "EQ",
	BlockMIPSNE:  "NE",
	BlockMIPSLTZ: "LTZ",
	BlockMIPSLEZ: "LEZ",
	BlockMIPSGTZ: "GTZ",
	BlockMIPSGEZ: "GEZ",
	BlockMIPSFPT: "FPT",
	BlockMIPSFPF: "FPF",

	BlockMIPS64EQ:  "EQ",
	BlockMIPS64NE:  "NE",
	BlockMIPS64LTZ: "LTZ",
	BlockMIPS64LEZ: "LEZ",
	BlockMIPS64GTZ: "GTZ",
	BlockMIPS64GEZ: "GEZ",
	BlockMIPS64FPT: "FPT",
	BlockMIPS64FPF: "FPF",

	BlockPPC64EQ:  "EQ",
	BlockPPC64NE:  "NE",
	BlockPPC64LT:  "LT",
	BlockPPC64LE:  "LE",
	BlockPPC64GT:  "GT",
	BlockPPC64GE:  "GE",
	BlockPPC64FLT: "FLT",
	BlockPPC64FLE: "FLE",
	BlockPPC64FGT: "FGT",
	BlockPPC64FGE: "FGE",

	BlockRISCV64BEQ:  "BEQ",
	BlockRISCV64BNE:  "BNE",
	BlockRISCV64BLT:  "BLT",
	BlockRISCV64BGE:  "BGE",
	BlockRISCV64BLTU: "BLTU",
	BlockRISCV64BGEU: "BGEU",
	BlockRISCV64BEQZ: "BEQZ",
	BlockRISCV64BNEZ: "BNEZ",
	BlockRISCV64BLEZ: "BLEZ",
	BlockRISCV64BGEZ: "BGEZ",
	BlockRISCV64BLTZ: "BLTZ",
	BlockRISCV64BGTZ: "BGTZ",

	BlockS390XBRC:   "BRC",
	BlockS390XCRJ:   "CRJ",
	BlockS390XCGRJ:  "CGRJ",
	BlockS390XCLRJ:  "CLRJ",
	BlockS390XCLGRJ: "CLGRJ",
	BlockS390XCIJ:   "CIJ",
	BlockS390XCGIJ:  "CGIJ",
	BlockS390XCLIJ:  "CLIJ",
	BlockS390XCLGIJ: "CLGIJ",

	BlockPlain:     "Plain",
	BlockIf:        "If",
	BlockDefer:     "Defer",
	BlockRet:       "Ret",
	BlockRetJmp:    "RetJmp",
	BlockExit:      "Exit",
	BlockJumpTable: "JumpTable",
	BlockFirst:     "First",
}

func (k BlockKind) String() string { return blockString[k] }
func (k BlockKind) AuxIntType() string {
	switch k {
	case BlockARM64TBZ:
		return "int64"
	case BlockARM64TBNZ:
		return "int64"
	case BlockS390XCIJ:
		return "int8"
	case BlockS390XCGIJ:
		return "int8"
	case BlockS390XCLIJ:
		return "uint8"
	case BlockS390XCLGIJ:
		return "uint8"
	}
	return ""
}

const (
	OpInvalid Op = iota

	Op386ADDSS
	Op386ADDSD
	Op386SUBSS
	Op386SUBSD
	Op386MULSS
	Op386MULSD
	Op386DIVSS
	Op386DIVSD
	Op386MOVSSload
	Op386MOVSDload
	Op386MOVSSconst
	Op386MOVSDconst
	Op386MOVSSloadidx1
	Op386MOVSSloadidx4
	Op386MOVSDloadidx1
	Op386MOVSDloadidx8
	Op386MOVSSstore
	Op386MOVSDstore
	Op386MOVSSstoreidx1
	Op386MOVSSstoreidx4
	Op386MOVSDstoreidx1
	Op386MOVSDstoreidx8
	Op386ADDSSload
	Op386ADDSDload
	Op386SUBSSload
	Op386SUBSDload
	Op386MULSSload
	Op386MULSDload
	Op386DIVSSload
	Op386DIVSDload
	Op386ADDL
	Op386ADDLconst
	Op386ADDLcarry
	Op386ADDLconstcarry
	Op386ADCL
	Op386ADCLcarry
	Op386ADCLconst
	Op386SUBL
	Op386SUBLconst
	Op386SUBLcarry
	Op386SUBLconstcarry
	Op386SBBL
	Op386SBBLconst
	Op386MULL
	Op386MULLconst
	Op386MULLU
	Op386HMULL
	Op386HMULLU
	Op386MULLQU
	Op386AVGLU
	Op386DIVL
	Op386DIVW
	Op386DIVLU
	Op386DIVWU
	Op386MODL
	Op386MODW
	Op386MODLU
	Op386MODWU
	Op386ANDL
	Op386ANDLconst
	Op386ORL
	Op386ORLconst
	Op386XORL
	Op386XORLconst
	Op386CMPL
	Op386CMPW
	Op386CMPB
	Op386CMPLconst
	Op386CMPWconst
	Op386CMPBconst
	Op386CMPLload
	Op386CMPWload
	Op386CMPBload
	Op386CMPLconstload
	Op386CMPWconstload
	Op386CMPBconstload
	Op386UCOMISS
	Op386UCOMISD
	Op386TESTL
	Op386TESTW
	Op386TESTB
	Op386TESTLconst
	Op386TESTWconst
	Op386TESTBconst
	Op386SHLL
	Op386SHLLconst
	Op386SHRL
	Op386SHRW
	Op386SHRB
	Op386SHRLconst
	Op386SHRWconst
	Op386SHRBconst
	Op386SARL
	Op386SARW
	Op386SARB
	Op386SARLconst
	Op386SARWconst
	Op386SARBconst
	Op386ROLL
	Op386ROLW
	Op386ROLB
	Op386ROLLconst
	Op386ROLWconst
	Op386ROLBconst
	Op386ADDLload
	Op386SUBLload
	Op386MULLload
	Op386ANDLload
	Op386ORLload
	Op386XORLload
	Op386ADDLloadidx4
	Op386SUBLloadidx4
	Op386MULLloadidx4
	Op386ANDLloadidx4
	Op386ORLloadidx4
	Op386XORLloadidx4
	Op386NEGL
	Op386NOTL
	Op386BSFL
	Op386BSFW
	Op386LoweredCtz32
	Op386LoweredCtz64
	Op386BSRL
	Op386BSRW
	Op386BSWAPL
	Op386SQRTSD
	Op386SQRTSS
	Op386SBBLcarrymask
	Op386SETEQ
	Op386SETNE
	Op386SETL
	Op386SETLE
	Op386SETG
	Op386SETGE
	Op386SETB
	Op386SETBE
	Op386SETA
	Op386SETAE
	Op386SETO
	Op386SETEQF
	Op386SETNEF
	Op386SETORD
	Op386SETNAN
	Op386SETGF
	Op386SETGEF
	Op386MOVBLSX
	Op386MOVBLZX
	Op386MOVWLSX
	Op386MOVWLZX
	Op386MOVLconst
	Op386CVTTSD2SL
	Op386CVTTSS2SL
	Op386CVTSL2SS
	Op386CVTSL2SD
	Op386CVTSD2SS
	Op386CVTSS2SD
	Op386PXOR
	Op386LEAL
	Op386LEAL1
	Op386LEAL2
	Op386LEAL4
	Op386LEAL8
	Op386MOVBload
	Op386MOVBLSXload
	Op386MOVWload
	Op386MOVWLSXload
	Op386MOVLload
	Op386MOVBstore
	Op386MOVWstore
	Op386MOVLstore
	Op386ADDLmodify
	Op386SUBLmodify
	Op386ANDLmodify
	Op386ORLmodify
	Op386XORLmodify
	Op386ADDLmodifyidx4
	Op386SUBLmodifyidx4
	Op386ANDLmodifyidx4
	Op386ORLmodifyidx4
	Op386XORLmodifyidx4
	Op386ADDLconstmodify
	Op386ANDLconstmodify
	Op386ORLconstmodify
	Op386XORLconstmodify
	Op386ADDLconstmodifyidx4
	Op386ANDLconstmodifyidx4
	Op386ORLconstmodifyidx4
	Op386XORLconstmodifyidx4
	Op386MOVBloadidx1
	Op386MOVWloadidx1
	Op386MOVWloadidx2
	Op386MOVLloadidx1
	Op386MOVLloadidx4
	Op386MOVBstoreidx1
	Op386MOVWstoreidx1
	Op386MOVWstoreidx2
	Op386MOVLstoreidx1
	Op386MOVLstoreidx4
	Op386MOVBstoreconst
	Op386MOVWstoreconst
	Op386MOVLstoreconst
	Op386MOVBstoreconstidx1
	Op386MOVWstoreconstidx1
	Op386MOVWstoreconstidx2
	Op386MOVLstoreconstidx1
	Op386MOVLstoreconstidx4
	Op386DUFFZERO
	Op386REPSTOSL
	Op386CALLstatic
	Op386CALLtail
	Op386CALLtailinter
	Op386CALLclosure
	Op386CALLinter
	Op386DUFFCOPY
	Op386REPMOVSL
	Op386InvertFlags
	Op386LoweredGetG
	Op386LoweredGetClosurePtr
	Op386LoweredGetCallerPC
	Op386LoweredGetCallerSP
	Op386LoweredNilCheck
	Op386LoweredWB
	Op386LoweredPanicBoundsRR
	Op386LoweredPanicBoundsRC
	Op386LoweredPanicBoundsCR
	Op386LoweredPanicBoundsCC
	Op386LoweredPanicExtendRR
	Op386LoweredPanicExtendRC
	Op386FlagEQ
	Op386FlagLT_ULT
	Op386FlagLT_UGT
	Op386FlagGT_UGT
	Op386FlagGT_ULT
	Op386MOVSSconst1
	Op386MOVSDconst1
	Op386MOVSSconst2
	Op386MOVSDconst2

	OpAMD64ADDSS
	OpAMD64ADDSD
	OpAMD64SUBSS
	OpAMD64SUBSD
	OpAMD64MULSS
	OpAMD64MULSD
	OpAMD64DIVSS
	OpAMD64DIVSD
	OpAMD64MOVSSload
	OpAMD64MOVSDload
	OpAMD64MOVSSconst
	OpAMD64MOVSDconst
	OpAMD64MOVSSloadidx1
	OpAMD64MOVSSloadidx4
	OpAMD64MOVSDloadidx1
	OpAMD64MOVSDloadidx8
	OpAMD64MOVSSstore
	OpAMD64MOVSDstore
	OpAMD64MOVSSstoreidx1
	OpAMD64MOVSSstoreidx4
	OpAMD64MOVSDstoreidx1
	OpAMD64MOVSDstoreidx8
	OpAMD64ADDSSload
	OpAMD64ADDSDload
	OpAMD64SUBSSload
	OpAMD64SUBSDload
	OpAMD64MULSSload
	OpAMD64MULSDload
	OpAMD64DIVSSload
	OpAMD64DIVSDload
	OpAMD64ADDSSloadidx1
	OpAMD64ADDSSloadidx4
	OpAMD64ADDSDloadidx1
	OpAMD64ADDSDloadidx8
	OpAMD64SUBSSloadidx1
	OpAMD64SUBSSloadidx4
	OpAMD64SUBSDloadidx1
	OpAMD64SUBSDloadidx8
	OpAMD64MULSSloadidx1
	OpAMD64MULSSloadidx4
	OpAMD64MULSDloadidx1
	OpAMD64MULSDloadidx8
	OpAMD64DIVSSloadidx1
	OpAMD64DIVSSloadidx4
	OpAMD64DIVSDloadidx1
	OpAMD64DIVSDloadidx8
	OpAMD64ADDQ
	OpAMD64ADDL
	OpAMD64ADDQconst
	OpAMD64ADDLconst
	OpAMD64ADDQconstmodify
	OpAMD64ADDLconstmodify
	OpAMD64SUBQ
	OpAMD64SUBL
	OpAMD64SUBQconst
	OpAMD64SUBLconst
	OpAMD64MULQ
	OpAMD64MULL
	OpAMD64MULQconst
	OpAMD64MULLconst
	OpAMD64MULLU
	OpAMD64MULQU
	OpAMD64HMULQ
	OpAMD64HMULL
	OpAMD64HMULQU
	OpAMD64HMULLU
	OpAMD64AVGQU
	OpAMD64DIVQ
	OpAMD64DIVL
	OpAMD64DIVW
	OpAMD64DIVQU
	OpAMD64DIVLU
	OpAMD64DIVWU
	OpAMD64NEGLflags
	OpAMD64ADDQconstflags
	OpAMD64ADDLconstflags
	OpAMD64ADDQcarry
	OpAMD64ADCQ
	OpAMD64ADDQconstcarry
	OpAMD64ADCQconst
	OpAMD64SUBQborrow
	OpAMD64SBBQ
	OpAMD64SUBQconstborrow
	OpAMD64SBBQconst
	OpAMD64MULQU2
	OpAMD64DIVQU2
	OpAMD64ANDQ
	OpAMD64ANDL
	OpAMD64ANDQconst
	OpAMD64ANDLconst
	OpAMD64ANDQconstmodify
	OpAMD64ANDLconstmodify
	OpAMD64ORQ
	OpAMD64ORL
	OpAMD64ORQconst
	OpAMD64ORLconst
	OpAMD64ORQconstmodify
	OpAMD64ORLconstmodify
	OpAMD64XORQ
	OpAMD64XORL
	OpAMD64XORQconst
	OpAMD64XORLconst
	OpAMD64XORQconstmodify
	OpAMD64XORLconstmodify
	OpAMD64CMPQ
	OpAMD64CMPL
	OpAMD64CMPW
	OpAMD64CMPB
	OpAMD64CMPQconst
	OpAMD64CMPLconst
	OpAMD64CMPWconst
	OpAMD64CMPBconst
	OpAMD64CMPQload
	OpAMD64CMPLload
	OpAMD64CMPWload
	OpAMD64CMPBload
	OpAMD64CMPQconstload
	OpAMD64CMPLconstload
	OpAMD64CMPWconstload
	OpAMD64CMPBconstload
	OpAMD64CMPQloadidx8
	OpAMD64CMPQloadidx1
	OpAMD64CMPLloadidx4
	OpAMD64CMPLloadidx1
	OpAMD64CMPWloadidx2
	OpAMD64CMPWloadidx1
	OpAMD64CMPBloadidx1
	OpAMD64CMPQconstloadidx8
	OpAMD64CMPQconstloadidx1
	OpAMD64CMPLconstloadidx4
	OpAMD64CMPLconstloadidx1
	OpAMD64CMPWconstloadidx2
	OpAMD64CMPWconstloadidx1
	OpAMD64CMPBconstloadidx1
	OpAMD64UCOMISS
	OpAMD64UCOMISD
	OpAMD64BTL
	OpAMD64BTQ
	OpAMD64BTCL
	OpAMD64BTCQ
	OpAMD64BTRL
	OpAMD64BTRQ
	OpAMD64BTSL
	OpAMD64BTSQ
	OpAMD64BTLconst
	OpAMD64BTQconst
	OpAMD64BTCQconst
	OpAMD64BTRQconst
	OpAMD64BTSQconst
	OpAMD64BTSQconstmodify
	OpAMD64BTRQconstmodify
	OpAMD64BTCQconstmodify
	OpAMD64TESTQ
	OpAMD64TESTL
	OpAMD64TESTW
	OpAMD64TESTB
	OpAMD64TESTQconst
	OpAMD64TESTLconst
	OpAMD64TESTWconst
	OpAMD64TESTBconst
	OpAMD64SHLQ
	OpAMD64SHLL
	OpAMD64SHLQconst
	OpAMD64SHLLconst
	OpAMD64SHRQ
	OpAMD64SHRL
	OpAMD64SHRW
	OpAMD64SHRB
	OpAMD64SHRQconst
	OpAMD64SHRLconst
	OpAMD64SHRWconst
	OpAMD64SHRBconst
	OpAMD64SARQ
	OpAMD64SARL
	OpAMD64SARW
	OpAMD64SARB
	OpAMD64SARQconst
	OpAMD64SARLconst
	OpAMD64SARWconst
	OpAMD64SARBconst
	OpAMD64ROLQ
	OpAMD64ROLL
	OpAMD64ROLW
	OpAMD64ROLB
	OpAMD64RORQ
	OpAMD64RORL
	OpAMD64RORW
	OpAMD64RORB
	OpAMD64ROLQconst
	OpAMD64ROLLconst
	OpAMD64ROLWconst
	OpAMD64ROLBconst
	OpAMD64ADDLload
	OpAMD64ADDQload
	OpAMD64SUBQload
	OpAMD64SUBLload
	OpAMD64ANDLload
	OpAMD64ANDQload
	OpAMD64ORQload
	OpAMD64ORLload
	OpAMD64XORQload
	OpAMD64XORLload
	OpAMD64ADDLloadidx1
	OpAMD64ADDLloadidx4
	OpAMD64ADDLloadidx8
	OpAMD64ADDQloadidx1
	OpAMD64ADDQloadidx8
	OpAMD64SUBLloadidx1
	OpAMD64SUBLloadidx4
	OpAMD64SUBLloadidx8
	OpAMD64SUBQloadidx1
	OpAMD64SUBQloadidx8
	OpAMD64ANDLloadidx1
	OpAMD64ANDLloadidx4
	OpAMD64ANDLloadidx8
	OpAMD64ANDQloadidx1
	OpAMD64ANDQloadidx8
	OpAMD64ORLloadidx1
	OpAMD64ORLloadidx4
	OpAMD64ORLloadidx8
	OpAMD64ORQloadidx1
	OpAMD64ORQloadidx8
	OpAMD64XORLloadidx1
	OpAMD64XORLloadidx4
	OpAMD64XORLloadidx8
	OpAMD64XORQloadidx1
	OpAMD64XORQloadidx8
	OpAMD64ADDQmodify
	OpAMD64SUBQmodify
	OpAMD64ANDQmodify
	OpAMD64ORQmodify
	OpAMD64XORQmodify
	OpAMD64ADDLmodify
	OpAMD64SUBLmodify
	OpAMD64ANDLmodify
	OpAMD64ORLmodify
	OpAMD64XORLmodify
	OpAMD64ADDQmodifyidx1
	OpAMD64ADDQmodifyidx8
	OpAMD64SUBQmodifyidx1
	OpAMD64SUBQmodifyidx8
	OpAMD64ANDQmodifyidx1
	OpAMD64ANDQmodifyidx8
	OpAMD64ORQmodifyidx1
	OpAMD64ORQmodifyidx8
	OpAMD64XORQmodifyidx1
	OpAMD64XORQmodifyidx8
	OpAMD64ADDLmodifyidx1
	OpAMD64ADDLmodifyidx4
	OpAMD64ADDLmodifyidx8
	OpAMD64SUBLmodifyidx1
	OpAMD64SUBLmodifyidx4
	OpAMD64SUBLmodifyidx8
	OpAMD64ANDLmodifyidx1
	OpAMD64ANDLmodifyidx4
	OpAMD64ANDLmodifyidx8
	OpAMD64ORLmodifyidx1
	OpAMD64ORLmodifyidx4
	OpAMD64ORLmodifyidx8
	OpAMD64XORLmodifyidx1
	OpAMD64XORLmodifyidx4
	OpAMD64XORLmodifyidx8
	OpAMD64ADDQconstmodifyidx1
	OpAMD64ADDQconstmodifyidx8
	OpAMD64ANDQconstmodifyidx1
	OpAMD64ANDQconstmodifyidx8
	OpAMD64ORQconstmodifyidx1
	OpAMD64ORQconstmodifyidx8
	OpAMD64XORQconstmodifyidx1
	OpAMD64XORQconstmodifyidx8
	OpAMD64ADDLconstmodifyidx1
	OpAMD64ADDLconstmodifyidx4
	OpAMD64ADDLconstmodifyidx8
	OpAMD64ANDLconstmodifyidx1
	OpAMD64ANDLconstmodifyidx4
	OpAMD64ANDLconstmodifyidx8
	OpAMD64ORLconstmodifyidx1
	OpAMD64ORLconstmodifyidx4
	OpAMD64ORLconstmodifyidx8
	OpAMD64XORLconstmodifyidx1
	OpAMD64XORLconstmodifyidx4
	OpAMD64XORLconstmodifyidx8
	OpAMD64NEGQ
	OpAMD64NEGL
	OpAMD64NOTQ
	OpAMD64NOTL
	OpAMD64BSFQ
	OpAMD64BSFL
	OpAMD64BSRQ
	OpAMD64BSRL
	OpAMD64CMOVQEQ
	OpAMD64CMOVQNE
	OpAMD64CMOVQLT
	OpAMD64CMOVQGT
	OpAMD64CMOVQLE
	OpAMD64CMOVQGE
	OpAMD64CMOVQLS
	OpAMD64CMOVQHI
	OpAMD64CMOVQCC
	OpAMD64CMOVQCS
	OpAMD64CMOVLEQ
	OpAMD64CMOVLNE
	OpAMD64CMOVLLT
	OpAMD64CMOVLGT
	OpAMD64CMOVLLE
	OpAMD64CMOVLGE
	OpAMD64CMOVLLS
	OpAMD64CMOVLHI
	OpAMD64CMOVLCC
	OpAMD64CMOVLCS
	OpAMD64CMOVWEQ
	OpAMD64CMOVWNE
	OpAMD64CMOVWLT
	OpAMD64CMOVWGT
	OpAMD64CMOVWLE
	OpAMD64CMOVWGE
	OpAMD64CMOVWLS
	OpAMD64CMOVWHI
	OpAMD64CMOVWCC
	OpAMD64CMOVWCS
	OpAMD64CMOVQEQF
	OpAMD64CMOVQNEF
	OpAMD64CMOVQGTF
	OpAMD64CMOVQGEF
	OpAMD64CMOVLEQF
	OpAMD64CMOVLNEF
	OpAMD64CMOVLGTF
	OpAMD64CMOVLGEF
	OpAMD64CMOVWEQF
	OpAMD64CMOVWNEF
	OpAMD64CMOVWGTF
	OpAMD64CMOVWGEF
	OpAMD64BSWAPQ
	OpAMD64BSWAPL
	OpAMD64POPCNTQ
	OpAMD64POPCNTL
	OpAMD64SQRTSD
	OpAMD64SQRTSS
	OpAMD64ROUNDSD
	OpAMD64ROUNDSS
	OpAMD64LoweredRound32F
	OpAMD64LoweredRound64F
	OpAMD64VFMADD231SS
	OpAMD64VFMADD231SD
	OpAMD64MINSD
	OpAMD64MINSS
	OpAMD64SBBQcarrymask
	OpAMD64SBBLcarrymask
	OpAMD64SETEQ
	OpAMD64SETNE
	OpAMD64SETL
	OpAMD64SETLE
	OpAMD64SETG
	OpAMD64SETGE
	OpAMD64SETB
	OpAMD64SETBE
	OpAMD64SETA
	OpAMD64SETAE
	OpAMD64SETO
	OpAMD64SETEQstore
	OpAMD64SETNEstore
	OpAMD64SETLstore
	OpAMD64SETLEstore
	OpAMD64SETGstore
	OpAMD64SETGEstore
	OpAMD64SETBstore
	OpAMD64SETBEstore
	OpAMD64SETAstore
	OpAMD64SETAEstore
	OpAMD64SETEQstoreidx1
	OpAMD64SETNEstoreidx1
	OpAMD64SETLstoreidx1
	OpAMD64SETLEstoreidx1
	OpAMD64SETGstoreidx1
	OpAMD64SETGEstoreidx1
	OpAMD64SETBstoreidx1
	OpAMD64SETBEstoreidx1
	OpAMD64SETAstoreidx1
	OpAMD64SETAEstoreidx1
	OpAMD64SETEQF
	OpAMD64SETNEF
	OpAMD64SETORD
	OpAMD64SETNAN
	OpAMD64SETGF
	OpAMD64SETGEF
	OpAMD64MOVBQSX
	OpAMD64MOVBQZX
	OpAMD64MOVWQSX
	OpAMD64MOVWQZX
	OpAMD64MOVLQSX
	OpAMD64MOVLQZX
	OpAMD64MOVLconst
	OpAMD64MOVQconst
	OpAMD64CVTTSD2SL
	OpAMD64CVTTSD2SQ
	OpAMD64CVTTSS2SL
	OpAMD64CVTTSS2SQ
	OpAMD64CVTSL2SS
	OpAMD64CVTSL2SD
	OpAMD64CVTSQ2SS
	OpAMD64CVTSQ2SD
	OpAMD64CVTSD2SS
	OpAMD64CVTSS2SD
	OpAMD64MOVQi2f
	OpAMD64MOVQf2i
	OpAMD64MOVLi2f
	OpAMD64MOVLf2i
	OpAMD64PXOR
	OpAMD64POR
	OpAMD64LEAQ
	OpAMD64LEAL
	OpAMD64LEAW
	OpAMD64LEAQ1
	OpAMD64LEAL1
	OpAMD64LEAW1
	OpAMD64LEAQ2
	OpAMD64LEAL2
	OpAMD64LEAW2
	OpAMD64LEAQ4
	OpAMD64LEAL4
	OpAMD64LEAW4
	OpAMD64LEAQ8
	OpAMD64LEAL8
	OpAMD64LEAW8
	OpAMD64MOVBload
	OpAMD64MOVBQSXload
	OpAMD64MOVWload
	OpAMD64MOVWQSXload
	OpAMD64MOVLload
	OpAMD64MOVLQSXload
	OpAMD64MOVQload
	OpAMD64MOVBstore
	OpAMD64MOVWstore
	OpAMD64MOVLstore
	OpAMD64MOVQstore
	OpAMD64MOVOload
	OpAMD64MOVOstore
	OpAMD64MOVBloadidx1
	OpAMD64MOVWloadidx1
	OpAMD64MOVWloadidx2
	OpAMD64MOVLloadidx1
	OpAMD64MOVLloadidx4
	OpAMD64MOVLloadidx8
	OpAMD64MOVQloadidx1
	OpAMD64MOVQloadidx8
	OpAMD64MOVBstoreidx1
	OpAMD64MOVWstoreidx1
	OpAMD64MOVWstoreidx2
	OpAMD64MOVLstoreidx1
	OpAMD64MOVLstoreidx4
	OpAMD64MOVLstoreidx8
	OpAMD64MOVQstoreidx1
	OpAMD64MOVQstoreidx8
	OpAMD64MOVBstoreconst
	OpAMD64MOVWstoreconst
	OpAMD64MOVLstoreconst
	OpAMD64MOVQstoreconst
	OpAMD64MOVOstoreconst
	OpAMD64MOVBstoreconstidx1
	OpAMD64MOVWstoreconstidx1
	OpAMD64MOVWstoreconstidx2
	OpAMD64MOVLstoreconstidx1
	OpAMD64MOVLstoreconstidx4
	OpAMD64MOVQstoreconstidx1
	OpAMD64MOVQstoreconstidx8
	OpAMD64LoweredZero
	OpAMD64LoweredZeroLoop
	OpAMD64REPSTOSQ
	OpAMD64CALLstatic
	OpAMD64CALLtail
	OpAMD64CALLtailinter
	OpAMD64CALLclosure
	OpAMD64CALLinter
	OpAMD64LoweredMove
	OpAMD64LoweredMoveLoop
	OpAMD64REPMOVSQ
	OpAMD64InvertFlags
	OpAMD64LoweredGetG
	OpAMD64LoweredGetClosurePtr
	OpAMD64LoweredGetCallerPC
	OpAMD64LoweredGetCallerSP
	OpAMD64LoweredNilCheck
	OpAMD64LoweredWB
	OpAMD64LoweredHasCPUFeature
	OpAMD64LoweredPanicBoundsRR
	OpAMD64LoweredPanicBoundsRC
	OpAMD64LoweredPanicBoundsCR
	OpAMD64LoweredPanicBoundsCC
	OpAMD64FlagEQ
	OpAMD64FlagLT_ULT
	OpAMD64FlagLT_UGT
	OpAMD64FlagGT_UGT
	OpAMD64FlagGT_ULT
	OpAMD64MOVBatomicload
	OpAMD64MOVLatomicload
	OpAMD64MOVQatomicload
	OpAMD64XCHGB
	OpAMD64XCHGL
	OpAMD64XCHGQ
	OpAMD64XADDLlock
	OpAMD64XADDQlock
	OpAMD64AddTupleFirst32
	OpAMD64AddTupleFirst64
	OpAMD64CMPXCHGLlock
	OpAMD64CMPXCHGQlock
	OpAMD64ANDBlock
	OpAMD64ANDLlock
	OpAMD64ANDQlock
	OpAMD64ORBlock
	OpAMD64ORLlock
	OpAMD64ORQlock
	OpAMD64LoweredAtomicAnd64
	OpAMD64LoweredAtomicAnd32
	OpAMD64LoweredAtomicOr64
	OpAMD64LoweredAtomicOr32
	OpAMD64PrefetchT0
	OpAMD64PrefetchNTA
	OpAMD64ANDNQ
	OpAMD64ANDNL
	OpAMD64BLSIQ
	OpAMD64BLSIL
	OpAMD64BLSMSKQ
	OpAMD64BLSMSKL
	OpAMD64BLSRQ
	OpAMD64BLSRL
	OpAMD64TZCNTQ
	OpAMD64TZCNTL
	OpAMD64LZCNTQ
	OpAMD64LZCNTL
	OpAMD64MOVBEWstore
	OpAMD64MOVBELload
	OpAMD64MOVBELstore
	OpAMD64MOVBEQload
	OpAMD64MOVBEQstore
	OpAMD64MOVBELloadidx1
	OpAMD64MOVBELloadidx4
	OpAMD64MOVBELloadidx8
	OpAMD64MOVBEQloadidx1
	OpAMD64MOVBEQloadidx8
	OpAMD64MOVBEWstoreidx1
	OpAMD64MOVBEWstoreidx2
	OpAMD64MOVBELstoreidx1
	OpAMD64MOVBELstoreidx4
	OpAMD64MOVBELstoreidx8
	OpAMD64MOVBEQstoreidx1
	OpAMD64MOVBEQstoreidx8
	OpAMD64SARXQ
	OpAMD64SARXL
	OpAMD64SHLXQ
	OpAMD64SHLXL
	OpAMD64SHRXQ
	OpAMD64SHRXL
	OpAMD64SARXLload
	OpAMD64SARXQload
	OpAMD64SHLXLload
	OpAMD64SHLXQload
	OpAMD64SHRXLload
	OpAMD64SHRXQload
	OpAMD64SARXLloadidx1
	OpAMD64SARXLloadidx4
	OpAMD64SARXLloadidx8
	OpAMD64SARXQloadidx1
	OpAMD64SARXQloadidx8
	OpAMD64SHLXLloadidx1
	OpAMD64SHLXLloadidx4
	OpAMD64SHLXLloadidx8
	OpAMD64SHLXQloadidx1
	OpAMD64SHLXQloadidx8
	OpAMD64SHRXLloadidx1
	OpAMD64SHRXLloadidx4
	OpAMD64SHRXLloadidx8
	OpAMD64SHRXQloadidx1
	OpAMD64SHRXQloadidx8
	OpAMD64PUNPCKLBW
	OpAMD64PSHUFLW
	OpAMD64PSHUFBbroadcast
	OpAMD64VPBROADCASTB
	OpAMD64PSIGNB
	OpAMD64PCMPEQB
	OpAMD64PMOVMSKB
	OpAMD64VMOVDQUload128
	OpAMD64VMOVDQUstore128
	OpAMD64VMOVDQUload256
	OpAMD64VMOVDQUstore256
	OpAMD64VMOVDQUload512
	OpAMD64VMOVDQUstore512
	OpAMD64VPMASK32load128
	OpAMD64VPMASK32store128
	OpAMD64VPMASK64load128
	OpAMD64VPMASK64store128
	OpAMD64VPMASK32load256
	OpAMD64VPMASK32store256
	OpAMD64VPMASK64load256
	OpAMD64VPMASK64store256
	OpAMD64VPMASK8load512
	OpAMD64VPMASK8store512
	OpAMD64VPMASK16load512
	OpAMD64VPMASK16store512
	OpAMD64VPMASK32load512
	OpAMD64VPMASK32store512
	OpAMD64VPMASK64load512
	OpAMD64VPMASK64store512
	OpAMD64VPMOVMToVec8x16
	OpAMD64VPMOVMToVec8x32
	OpAMD64VPMOVMToVec8x64
	OpAMD64VPMOVMToVec16x8
	OpAMD64VPMOVMToVec16x16
	OpAMD64VPMOVMToVec16x32
	OpAMD64VPMOVMToVec32x4
	OpAMD64VPMOVMToVec32x8
	OpAMD64VPMOVMToVec32x16
	OpAMD64VPMOVMToVec64x2
	OpAMD64VPMOVMToVec64x4
	OpAMD64VPMOVMToVec64x8
	OpAMD64VPMOVVec8x16ToM
	OpAMD64VPMOVVec8x32ToM
	OpAMD64VPMOVVec8x64ToM
	OpAMD64VPMOVVec16x8ToM
	OpAMD64VPMOVVec16x16ToM
	OpAMD64VPMOVVec16x32ToM
	OpAMD64VPMOVVec32x4ToM
	OpAMD64VPMOVVec32x8ToM
	OpAMD64VPMOVVec32x16ToM
	OpAMD64VPMOVVec64x2ToM
	OpAMD64VPMOVVec64x4ToM
	OpAMD64VPMOVVec64x8ToM
	OpAMD64VPMOVMSKB128
	OpAMD64VPMOVMSKB256
	OpAMD64VMOVMSKPS128
	OpAMD64VMOVMSKPS256
	OpAMD64VMOVMSKPD128
	OpAMD64VMOVMSKPD256
	OpAMD64Zero128
	OpAMD64Zero256
	OpAMD64Zero512
	OpAMD64VMOVSDf2v
	OpAMD64VMOVSSf2v
	OpAMD64VMOVQ
	OpAMD64VMOVD
	OpAMD64VMOVQload
	OpAMD64VMOVDload
	OpAMD64VMOVSSload
	OpAMD64VMOVSDload
	OpAMD64VMOVSSconst
	OpAMD64VMOVSDconst
	OpAMD64VZEROUPPER
	OpAMD64VZEROALL
	OpAMD64KMOVBload
	OpAMD64KMOVWload
	OpAMD64KMOVDload
	OpAMD64KMOVQload
	OpAMD64KMOVBstore
	OpAMD64KMOVWstore
	OpAMD64KMOVDstore
	OpAMD64KMOVQstore
	OpAMD64KMOVQk
	OpAMD64KMOVDk
	OpAMD64KMOVWk
	OpAMD64KMOVBk
	OpAMD64KMOVQi
	OpAMD64KMOVDi
	OpAMD64KMOVWi
	OpAMD64KMOVBi
	OpAMD64KANDB
	OpAMD64KANDW
	OpAMD64KANDD
	OpAMD64KANDQ
	OpAMD64KORB
	OpAMD64KORW
	OpAMD64KORD
	OpAMD64KORQ
	OpAMD64KXORB
	OpAMD64KXORW
	OpAMD64KXORD
	OpAMD64KXORQ
	OpAMD64KXNORB
	OpAMD64KXNORW
	OpAMD64KXNORD
	OpAMD64KXNORQ
	OpAMD64VPTEST
	OpAMD64SHA1MSG1128
	OpAMD64SHA1MSG2128
	OpAMD64SHA1NEXTE128
	OpAMD64SHA256MSG1128
	OpAMD64SHA256MSG2128
	OpAMD64SHA256RNDS2128
	OpAMD64VADDPD128
	OpAMD64VADDPD256
	OpAMD64VADDPD512
	OpAMD64VADDPDMasked128
	OpAMD64VADDPDMasked256
	OpAMD64VADDPDMasked512
	OpAMD64VADDPS128
	OpAMD64VADDPS256
	OpAMD64VADDPS512
	OpAMD64VADDPSMasked128
	OpAMD64VADDPSMasked256
	OpAMD64VADDPSMasked512
	OpAMD64VADDSUBPD128
	OpAMD64VADDSUBPD256
	OpAMD64VADDSUBPS128
	OpAMD64VADDSUBPS256
	OpAMD64VAESDEC128
	OpAMD64VAESDEC256
	OpAMD64VAESDEC512
	OpAMD64VAESDECLAST128
	OpAMD64VAESDECLAST256
	OpAMD64VAESDECLAST512
	OpAMD64VAESENC128
	OpAMD64VAESENC256
	OpAMD64VAESENC512
	OpAMD64VAESENCLAST128
	OpAMD64VAESENCLAST256
	OpAMD64VAESENCLAST512
	OpAMD64VAESIMC128
	OpAMD64VBROADCASTSD256
	OpAMD64VBROADCASTSD512
	OpAMD64VBROADCASTSDMasked256
	OpAMD64VBROADCASTSDMasked512
	OpAMD64VBROADCASTSS128
	OpAMD64VBROADCASTSS256
	OpAMD64VBROADCASTSS512
	OpAMD64VBROADCASTSSMasked128
	OpAMD64VBROADCASTSSMasked256
	OpAMD64VBROADCASTSSMasked512
	OpAMD64VCOMPRESSPDMasked128
	OpAMD64VCOMPRESSPDMasked256
	OpAMD64VCOMPRESSPDMasked512
	OpAMD64VCOMPRESSPSMasked128
	OpAMD64VCOMPRESSPSMasked256
	OpAMD64VCOMPRESSPSMasked512
	OpAMD64VCVTDQ2PD256
	OpAMD64VCVTDQ2PD512
	OpAMD64VCVTDQ2PDMasked256
	OpAMD64VCVTDQ2PDMasked512
	OpAMD64VCVTDQ2PS128
	OpAMD64VCVTDQ2PS256
	OpAMD64VCVTDQ2PS512
	OpAMD64VCVTDQ2PSMasked128
	OpAMD64VCVTDQ2PSMasked256
	OpAMD64VCVTDQ2PSMasked512
	OpAMD64VCVTPD2PS256
	OpAMD64VCVTPD2PSMasked256
	OpAMD64VCVTPD2PSX128
	OpAMD64VCVTPD2PSXMasked128
	OpAMD64VCVTPD2PSY128
	OpAMD64VCVTPD2PSYMasked128
	OpAMD64VCVTPS2PD256
	OpAMD64VCVTPS2PD512
	OpAMD64VCVTPS2PDMasked256
	OpAMD64VCVTPS2PDMasked512
	OpAMD64VCVTQQ2PD128
	OpAMD64VCVTQQ2PD256
	OpAMD64VCVTQQ2PD512
	OpAMD64VCVTQQ2PDMasked128
	OpAMD64VCVTQQ2PDMasked256
	OpAMD64VCVTQQ2PDMasked512
	OpAMD64VCVTQQ2PS256
	OpAMD64VCVTQQ2PSMasked256
	OpAMD64VCVTQQ2PSX128
	OpAMD64VCVTQQ2PSXMasked128
	OpAMD64VCVTQQ2PSY128
	OpAMD64VCVTQQ2PSYMasked128
	OpAMD64VCVTTPD2DQ256
	OpAMD64VCVTTPD2DQMasked256
	OpAMD64VCVTTPD2DQX128
	OpAMD64VCVTTPD2DQXMasked128
	OpAMD64VCVTTPD2DQY128
	OpAMD64VCVTTPD2DQYMasked128
	OpAMD64VCVTTPD2QQ128
	OpAMD64VCVTTPD2QQ256
	OpAMD64VCVTTPD2QQ512
	OpAMD64VCVTTPD2QQMasked128
	OpAMD64VCVTTPD2QQMasked256
	OpAMD64VCVTTPD2QQMasked512
	OpAMD64VCVTTPD2UDQ256
	OpAMD64VCVTTPD2UDQMasked256
	OpAMD64VCVTTPD2UDQX128
	OpAMD64VCVTTPD2UDQXMasked128
	OpAMD64VCVTTPD2UDQY128
	OpAMD64VCVTTPD2UDQYMasked128
	OpAMD64VCVTTPD2UQQ128
	OpAMD64VCVTTPD2UQQ256
	OpAMD64VCVTTPD2UQQ512
	OpAMD64VCVTTPD2UQQMasked128
	OpAMD64VCVTTPD2UQQMasked256
	OpAMD64VCVTTPD2UQQMasked512
	OpAMD64VCVTTPS2DQ128
	OpAMD64VCVTTPS2DQ256
	OpAMD64VCVTTPS2DQ512
	OpAMD64VCVTTPS2DQMasked128
	OpAMD64VCVTTPS2DQMasked256
	OpAMD64VCVTTPS2DQMasked512
	OpAMD64VCVTTPS2QQ256
	OpAMD64VCVTTPS2QQ512
	OpAMD64VCVTTPS2QQMasked256
	OpAMD64VCVTTPS2QQMasked512
	OpAMD64VCVTTPS2UDQ128
	OpAMD64VCVTTPS2UDQ256
	OpAMD64VCVTTPS2UDQ512
	OpAMD64VCVTTPS2UDQMasked128
	OpAMD64VCVTTPS2UDQMasked256
	OpAMD64VCVTTPS2UDQMasked512
	OpAMD64VCVTTPS2UQQ256
	OpAMD64VCVTTPS2UQQ512
	OpAMD64VCVTTPS2UQQMasked256
	OpAMD64VCVTTPS2UQQMasked512
	OpAMD64VCVTUDQ2PD256
	OpAMD64VCVTUDQ2PD512
	OpAMD64VCVTUDQ2PDMasked256
	OpAMD64VCVTUDQ2PDMasked512
	OpAMD64VCVTUDQ2PS128
	OpAMD64VCVTUDQ2PS256
	OpAMD64VCVTUDQ2PS512
	OpAMD64VCVTUDQ2PSMasked128
	OpAMD64VCVTUDQ2PSMasked256
	OpAMD64VCVTUDQ2PSMasked512
	OpAMD64VCVTUQQ2PD128
	OpAMD64VCVTUQQ2PD256
	OpAMD64VCVTUQQ2PD512
	OpAMD64VCVTUQQ2PDMasked128
	OpAMD64VCVTUQQ2PDMasked256
	OpAMD64VCVTUQQ2PDMasked512
	OpAMD64VCVTUQQ2PS256
	OpAMD64VCVTUQQ2PSMasked256
	OpAMD64VCVTUQQ2PSX128
	OpAMD64VCVTUQQ2PSXMasked128
	OpAMD64VCVTUQQ2PSY128
	OpAMD64VCVTUQQ2PSYMasked128
	OpAMD64VDIVPD128
	OpAMD64VDIVPD256
	OpAMD64VDIVPD512
	OpAMD64VDIVPDMasked128
	OpAMD64VDIVPDMasked256
	OpAMD64VDIVPDMasked512
	OpAMD64VDIVPS128
	OpAMD64VDIVPS256
	OpAMD64VDIVPS512
	OpAMD64VDIVPSMasked128
	OpAMD64VDIVPSMasked256
	OpAMD64VDIVPSMasked512
	OpAMD64VEXPANDPDMasked128
	OpAMD64VEXPANDPDMasked256
	OpAMD64VEXPANDPDMasked512
	OpAMD64VEXPANDPSMasked128
	OpAMD64VEXPANDPSMasked256
	OpAMD64VEXPANDPSMasked512
	OpAMD64VFMADD213PD128
	OpAMD64VFMADD213PD256
	OpAMD64VFMADD213PD512
	OpAMD64VFMADD213PDMasked128
	OpAMD64VFMADD213PDMasked256
	OpAMD64VFMADD213PDMasked512
	OpAMD64VFMADD213PS128
	OpAMD64VFMADD213PS256
	OpAMD64VFMADD213PS512
	OpAMD64VFMADD213PSMasked128
	OpAMD64VFMADD213PSMasked256
	OpAMD64VFMADD213PSMasked512
	OpAMD64VFMADDSUB213PD128
	OpAMD64VFMADDSUB213PD256
	OpAMD64VFMADDSUB213PD512
	OpAMD64VFMADDSUB213PDMasked128
	OpAMD64VFMADDSUB213PDMasked256
	OpAMD64VFMADDSUB213PDMasked512
	OpAMD64VFMADDSUB213PS128
	OpAMD64VFMADDSUB213PS256
	OpAMD64VFMADDSUB213PS512
	OpAMD64VFMADDSUB213PSMasked128
	OpAMD64VFMADDSUB213PSMasked256
	OpAMD64VFMADDSUB213PSMasked512
	OpAMD64VFMSUBADD213PD128
	OpAMD64VFMSUBADD213PD256
	OpAMD64VFMSUBADD213PD512
	OpAMD64VFMSUBADD213PDMasked128
	OpAMD64VFMSUBADD213PDMasked256
	OpAMD64VFMSUBADD213PDMasked512
	OpAMD64VFMSUBADD213PS128
	OpAMD64VFMSUBADD213PS256
	OpAMD64VFMSUBADD213PS512
	OpAMD64VFMSUBADD213PSMasked128
	OpAMD64VFMSUBADD213PSMasked256
	OpAMD64VFMSUBADD213PSMasked512
	OpAMD64VGF2P8MULB128
	OpAMD64VGF2P8MULB256
	OpAMD64VGF2P8MULB512
	OpAMD64VGF2P8MULBMasked128
	OpAMD64VGF2P8MULBMasked256
	OpAMD64VGF2P8MULBMasked512
	OpAMD64VHADDPD128
	OpAMD64VHADDPD256
	OpAMD64VHADDPS128
	OpAMD64VHADDPS256
	OpAMD64VHSUBPD128
	OpAMD64VHSUBPD256
	OpAMD64VHSUBPS128
	OpAMD64VHSUBPS256
	OpAMD64VMAXPD128
	OpAMD64VMAXPD256
	OpAMD64VMAXPD512
	OpAMD64VMAXPDMasked128
	OpAMD64VMAXPDMasked256
	OpAMD64VMAXPDMasked512
	OpAMD64VMAXPS128
	OpAMD64VMAXPS256
	OpAMD64VMAXPS512
	OpAMD64VMAXPSMasked128
	OpAMD64VMAXPSMasked256
	OpAMD64VMAXPSMasked512
	OpAMD64VMINPD128
	OpAMD64VMINPD256
	OpAMD64VMINPD512
	OpAMD64VMINPDMasked128
	OpAMD64VMINPDMasked256
	OpAMD64VMINPDMasked512
	OpAMD64VMINPS128
	OpAMD64VMINPS256
	OpAMD64VMINPS512
	OpAMD64VMINPSMasked128
	OpAMD64VMINPSMasked256
	OpAMD64VMINPSMasked512
	OpAMD64VMOVDQU8Masked128
	OpAMD64VMOVDQU8Masked256
	OpAMD64VMOVDQU8Masked512
	OpAMD64VMOVDQU16Masked128
	OpAMD64VMOVDQU16Masked256
	OpAMD64VMOVDQU16Masked512
	OpAMD64VMOVDQU32Masked128
	OpAMD64VMOVDQU32Masked256
	OpAMD64VMOVDQU32Masked512
	OpAMD64VMOVDQU64Masked128
	OpAMD64VMOVDQU64Masked256
	OpAMD64VMOVDQU64Masked512
	OpAMD64VMULPD128
	OpAMD64VMULPD256
	OpAMD64VMULPD512
	OpAMD64VMULPDMasked128
	OpAMD64VMULPDMasked256
	OpAMD64VMULPDMasked512
	OpAMD64VMULPS128
	OpAMD64VMULPS256
	OpAMD64VMULPS512
	OpAMD64VMULPSMasked128
	OpAMD64VMULPSMasked256
	OpAMD64VMULPSMasked512
	OpAMD64VPABSB128
	OpAMD64VPABSB256
	OpAMD64VPABSB512
	OpAMD64VPABSBMasked128
	OpAMD64VPABSBMasked256
	OpAMD64VPABSBMasked512
	OpAMD64VPABSD128
	OpAMD64VPABSD256
	OpAMD64VPABSD512
	OpAMD64VPABSDMasked128
	OpAMD64VPABSDMasked256
	OpAMD64VPABSDMasked512
	OpAMD64VPABSQ128
	OpAMD64VPABSQ256
	OpAMD64VPABSQ512
	OpAMD64VPABSQMasked128
	OpAMD64VPABSQMasked256
	OpAMD64VPABSQMasked512
	OpAMD64VPABSW128
	OpAMD64VPABSW256
	OpAMD64VPABSW512
	OpAMD64VPABSWMasked128
	OpAMD64VPABSWMasked256
	OpAMD64VPABSWMasked512
	OpAMD64VPACKSSDW128
	OpAMD64VPACKSSDW256
	OpAMD64VPACKSSDW512
	OpAMD64VPACKSSDWMasked128
	OpAMD64VPACKSSDWMasked256
	OpAMD64VPACKSSDWMasked512
	OpAMD64VPACKUSDW128
	OpAMD64VPACKUSDW256
	OpAMD64VPACKUSDW512
	OpAMD64VPACKUSDWMasked128
	OpAMD64VPACKUSDWMasked256
	OpAMD64VPACKUSDWMasked512
	OpAMD64VPADDB128
	OpAMD64VPADDB256
	OpAMD64VPADDB512
	OpAMD64VPADDBMasked128
	OpAMD64VPADDBMasked256
	OpAMD64VPADDBMasked512
	OpAMD64VPADDD128
	OpAMD64VPADDD256
	OpAMD64VPADDD512
	OpAMD64VPADDDMasked128
	OpAMD64VPADDDMasked256
	OpAMD64VPADDDMasked512
	OpAMD64VPADDQ128
	OpAMD64VPADDQ256
	OpAMD64VPADDQ512
	OpAMD64VPADDQMasked128
	OpAMD64VPADDQMasked256
	OpAMD64VPADDQMasked512
	OpAMD64VPADDSB128
	OpAMD64VPADDSB256
	OpAMD64VPADDSB512
	OpAMD64VPADDSBMasked128
	OpAMD64VPADDSBMasked256
	OpAMD64VPADDSBMasked512
	OpAMD64VPADDSW128
	OpAMD64VPADDSW256
	OpAMD64VPADDSW512
	OpAMD64VPADDSWMasked128
	OpAMD64VPADDSWMasked256
	OpAMD64VPADDSWMasked512
	OpAMD64VPADDUSB128
	OpAMD64VPADDUSB256
	OpAMD64VPADDUSB512
	OpAMD64VPADDUSBMasked128
	OpAMD64VPADDUSBMasked256
	OpAMD64VPADDUSBMasked512
	OpAMD64VPADDUSW128
	OpAMD64VPADDUSW256
	OpAMD64VPADDUSW512
	OpAMD64VPADDUSWMasked128
	OpAMD64VPADDUSWMasked256
	OpAMD64VPADDUSWMasked512
	OpAMD64VPADDW128
	OpAMD64VPADDW256
	OpAMD64VPADDW512
	OpAMD64VPADDWMasked128
	OpAMD64VPADDWMasked256
	OpAMD64VPADDWMasked512
	OpAMD64VPAND128
	OpAMD64VPAND256
	OpAMD64VPANDD512
	OpAMD64VPANDDMasked128
	OpAMD64VPANDDMasked256
	OpAMD64VPANDDMasked512
	OpAMD64VPANDN128
	OpAMD64VPANDN256
	OpAMD64VPANDND512
	OpAMD64VPANDNDMasked128
	OpAMD64VPANDNDMasked256
	OpAMD64VPANDNDMasked512
	OpAMD64VPANDNQ512
	OpAMD64VPANDNQMasked128
	OpAMD64VPANDNQMasked256
	OpAMD64VPANDNQMasked512
	OpAMD64VPANDQ512
	OpAMD64VPANDQMasked128
	OpAMD64VPANDQMasked256
	OpAMD64VPANDQMasked512
	OpAMD64VPAVGB128
	OpAMD64VPAVGB256
	OpAMD64VPAVGB512
	OpAMD64VPAVGBMasked128
	OpAMD64VPAVGBMasked256
	OpAMD64VPAVGBMasked512
	OpAMD64VPAVGW128
	OpAMD64VPAVGW256
	OpAMD64VPAVGW512
	OpAMD64VPAVGWMasked128
	OpAMD64VPAVGWMasked256
	OpAMD64VPAVGWMasked512
	OpAMD64VPBLENDMBMasked512
	OpAMD64VPBLENDMDMasked512
	OpAMD64VPBLENDMQMasked512
	OpAMD64VPBLENDMWMasked512
	OpAMD64VPBLENDVB128
	OpAMD64VPBLENDVB256
	OpAMD64VPBROADCASTB128
	OpAMD64VPBROADCASTB256
	OpAMD64VPBROADCASTB512
	OpAMD64VPBROADCASTBMasked128
	OpAMD64VPBROADCASTBMasked256
	OpAMD64VPBROADCASTBMasked512
	OpAMD64VPBROADCASTD128
	OpAMD64VPBROADCASTD256
	OpAMD64VPBROADCASTD512
	OpAMD64VPBROADCASTDMasked128
	OpAMD64VPBROADCASTDMasked256
	OpAMD64VPBROADCASTDMasked512
	OpAMD64VPBROADCASTQ128
	OpAMD64VPBROADCASTQ256
	OpAMD64VPBROADCASTQ512
	OpAMD64VPBROADCASTQMasked128
	OpAMD64VPBROADCASTQMasked256
	OpAMD64VPBROADCASTQMasked512
	OpAMD64VPBROADCASTW128
	OpAMD64VPBROADCASTW256
	OpAMD64VPBROADCASTW512
	OpAMD64VPBROADCASTWMasked128
	OpAMD64VPBROADCASTWMasked256
	OpAMD64VPBROADCASTWMasked512
	OpAMD64VPCMPEQB128
	OpAMD64VPCMPEQB256
	OpAMD64VPCMPEQB512
	OpAMD64VPCMPEQD128
	OpAMD64VPCMPEQD256
	OpAMD64VPCMPEQD512
	OpAMD64VPCMPEQQ128
	OpAMD64VPCMPEQQ256
	OpAMD64VPCMPEQQ512
	OpAMD64VPCMPEQW128
	OpAMD64VPCMPEQW256
	OpAMD64VPCMPEQW512
	OpAMD64VPCMPGTB128
	OpAMD64VPCMPGTB256
	OpAMD64VPCMPGTB512
	OpAMD64VPCMPGTD128
	OpAMD64VPCMPGTD256
	OpAMD64VPCMPGTD512
	OpAMD64VPCMPGTQ128
	OpAMD64VPCMPGTQ256
	OpAMD64VPCMPGTQ512
	OpAMD64VPCMPGTW128
	OpAMD64VPCMPGTW256
	OpAMD64VPCMPGTW512
	OpAMD64VPCOMPRESSBMasked128
	OpAMD64VPCOMPRESSBMasked256
	OpAMD64VPCOMPRESSBMasked512
	OpAMD64VPCOMPRESSDMasked128
	OpAMD64VPCOMPRESSDMasked256
	OpAMD64VPCOMPRESSDMasked512
	OpAMD64VPCOMPRESSQMasked128
	OpAMD64VPCOMPRESSQMasked256
	OpAMD64VPCOMPRESSQMasked512
	OpAMD64VPCOMPRESSWMasked128
	OpAMD64VPCOMPRESSWMasked256
	OpAMD64VPCOMPRESSWMasked512
	OpAMD64VPDPWSSD128
	OpAMD64VPDPWSSD256
	OpAMD64VPDPWSSD512
	OpAMD64VPDPWSSDMasked128
	OpAMD64VPDPWSSDMasked256
	OpAMD64VPDPWSSDMasked512
	OpAMD64VPERMB128
	OpAMD64VPERMB256
	OpAMD64VPERMB512
	OpAMD64VPERMBMasked128
	OpAMD64VPERMBMasked256
	OpAMD64VPERMBMasked512
	OpAMD64VPERMD256
	OpAMD64VPERMD512
	OpAMD64VPERMDMasked256
	OpAMD64VPERMDMasked512
	OpAMD64VPERMI2B128
	OpAMD64VPERMI2B256
	OpAMD64VPERMI2B512
	OpAMD64VPERMI2BMasked128
	OpAMD64VPERMI2BMasked256
	OpAMD64VPERMI2BMasked512
	OpAMD64VPERMI2D128
	OpAMD64VPERMI2D256
	OpAMD64VPERMI2D512
	OpAMD64VPERMI2DMasked128
	OpAMD64VPERMI2DMasked256
	OpAMD64VPERMI2DMasked512
	OpAMD64VPERMI2PD128
	OpAMD64VPERMI2PD256
	OpAMD64VPERMI2PD512
	OpAMD64VPERMI2PDMasked128
	OpAMD64VPERMI2PDMasked256
	OpAMD64VPERMI2PDMasked512
	OpAMD64VPERMI2PS128
	OpAMD64VPERMI2PS256
	OpAMD64VPERMI2PS512
	OpAMD64VPERMI2PSMasked128
	OpAMD64VPERMI2PSMasked256
	OpAMD64VPERMI2PSMasked512
	OpAMD64VPERMI2Q128
	OpAMD64VPERMI2Q256
	OpAMD64VPERMI2Q512
	OpAMD64VPERMI2QMasked128
	OpAMD64VPERMI2QMasked256
	OpAMD64VPERMI2QMasked512
	OpAMD64VPERMI2W128
	OpAMD64VPERMI2W256
	OpAMD64VPERMI2W512
	OpAMD64VPERMI2WMasked128
	OpAMD64VPERMI2WMasked256
	OpAMD64VPERMI2WMasked512
	OpAMD64VPERMPD256
	OpAMD64VPERMPD512
	OpAMD64VPERMPDMasked256
	OpAMD64VPERMPDMasked512
	OpAMD64VPERMPS256
	OpAMD64VPERMPS512
	OpAMD64VPERMPSMasked256
	OpAMD64VPERMPSMasked512
	OpAMD64VPERMQ256
	OpAMD64VPERMQ512
	OpAMD64VPERMQMasked256
	OpAMD64VPERMQMasked512
	OpAMD64VPERMW128
	OpAMD64VPERMW256
	OpAMD64VPERMW512
	OpAMD64VPERMWMasked128
	OpAMD64VPERMWMasked256
	OpAMD64VPERMWMasked512
	OpAMD64VPEXPANDBMasked128
	OpAMD64VPEXPANDBMasked256
	OpAMD64VPEXPANDBMasked512
	OpAMD64VPEXPANDDMasked128
	OpAMD64VPEXPANDDMasked256
	OpAMD64VPEXPANDDMasked512
	OpAMD64VPEXPANDQMasked128
	OpAMD64VPEXPANDQMasked256
	OpAMD64VPEXPANDQMasked512
	OpAMD64VPEXPANDWMasked128
	OpAMD64VPEXPANDWMasked256
	OpAMD64VPEXPANDWMasked512
	OpAMD64VPHADDD128
	OpAMD64VPHADDD256
	OpAMD64VPHADDSW128
	OpAMD64VPHADDSW256
	OpAMD64VPHADDW128
	OpAMD64VPHADDW256
	OpAMD64VPHSUBD128
	OpAMD64VPHSUBD256
	OpAMD64VPHSUBSW128
	OpAMD64VPHSUBSW256
	OpAMD64VPHSUBW128
	OpAMD64VPHSUBW256
	OpAMD64VPLZCNTD128
	OpAMD64VPLZCNTD256
	OpAMD64VPLZCNTD512
	OpAMD64VPLZCNTDMasked128
	OpAMD64VPLZCNTDMasked256
	OpAMD64VPLZCNTDMasked512
	OpAMD64VPLZCNTQ128
	OpAMD64VPLZCNTQ256
	OpAMD64VPLZCNTQ512
	OpAMD64VPLZCNTQMasked128
	OpAMD64VPLZCNTQMasked256
	OpAMD64VPLZCNTQMasked512
	OpAMD64VPMADDUBSW128
	OpAMD64VPMADDUBSW256
	OpAMD64VPMADDUBSW512
	OpAMD64VPMADDUBSWMasked128
	OpAMD64VPMADDUBSWMasked256
	OpAMD64VPMADDUBSWMasked512
	OpAMD64VPMADDWD128
	OpAMD64VPMADDWD256
	OpAMD64VPMADDWD512
	OpAMD64VPMADDWDMasked128
	OpAMD64VPMADDWDMasked256
	OpAMD64VPMADDWDMasked512
	OpAMD64VPMAXSB128
	OpAMD64VPMAXSB256
	OpAMD64VPMAXSB512
	OpAMD64VPMAXSBMasked128
	OpAMD64VPMAXSBMasked256
	OpAMD64VPMAXSBMasked512
	OpAMD64VPMAXSD128
	OpAMD64VPMAXSD256
	OpAMD64VPMAXSD512
	OpAMD64VPMAXSDMasked128
	OpAMD64VPMAXSDMasked256
	OpAMD64VPMAXSDMasked512
	OpAMD64VPMAXSQ128
	OpAMD64VPMAXSQ256
	OpAMD64VPMAXSQ512
	OpAMD64VPMAXSQMasked128
	OpAMD64VPMAXSQMasked256
	OpAMD64VPMAXSQMasked512
	OpAMD64VPMAXSW128
	OpAMD64VPMAXSW256
	OpAMD64VPMAXSW512
	OpAMD64VPMAXSWMasked128
	OpAMD64VPMAXSWMasked256
	OpAMD64VPMAXSWMasked512
	OpAMD64VPMAXUB128
	OpAMD64VPMAXUB256
	OpAMD64VPMAXUB512
	OpAMD64VPMAXUBMasked128
	OpAMD64VPMAXUBMasked256
	OpAMD64VPMAXUBMasked512
	OpAMD64VPMAXUD128
	OpAMD64VPMAXUD256
	OpAMD64VPMAXUD512
	OpAMD64VPMAXUDMasked128
	OpAMD64VPMAXUDMasked256
	OpAMD64VPMAXUDMasked512
	OpAMD64VPMAXUQ128
	OpAMD64VPMAXUQ256
	OpAMD64VPMAXUQ512
	OpAMD64VPMAXUQMasked128
	OpAMD64VPMAXUQMasked256
	OpAMD64VPMAXUQMasked512
	OpAMD64VPMAXUW128
	OpAMD64VPMAXUW256
	OpAMD64VPMAXUW512
	OpAMD64VPMAXUWMasked128
	OpAMD64VPMAXUWMasked256
	OpAMD64VPMAXUWMasked512
	OpAMD64VPMINSB128
	OpAMD64VPMINSB256
	OpAMD64VPMINSB512
	OpAMD64VPMINSBMasked128
	OpAMD64VPMINSBMasked256
	OpAMD64VPMINSBMasked512
	OpAMD64VPMINSD128
	OpAMD64VPMINSD256
	OpAMD64VPMINSD512
	OpAMD64VPMINSDMasked128
	OpAMD64VPMINSDMasked256
	OpAMD64VPMINSDMasked512
	OpAMD64VPMINSQ128
	OpAMD64VPMINSQ256
	OpAMD64VPMINSQ512
	OpAMD64VPMINSQMasked128
	OpAMD64VPMINSQMasked256
	OpAMD64VPMINSQMasked512
	OpAMD64VPMINSW128
	OpAMD64VPMINSW256
	OpAMD64VPMINSW512
	OpAMD64VPMINSWMasked128
	OpAMD64VPMINSWMasked256
	OpAMD64VPMINSWMasked512
	OpAMD64VPMINUB128
	OpAMD64VPMINUB256
	OpAMD64VPMINUB512
	OpAMD64VPMINUBMasked128
	OpAMD64VPMINUBMasked256
	OpAMD64VPMINUBMasked512
	OpAMD64VPMINUD128
	OpAMD64VPMINUD256
	OpAMD64VPMINUD512
	OpAMD64VPMINUDMasked128
	OpAMD64VPMINUDMasked256
	OpAMD64VPMINUDMasked512
	OpAMD64VPMINUQ128
	OpAMD64VPMINUQ256
	OpAMD64VPMINUQ512
	OpAMD64VPMINUQMasked128
	OpAMD64VPMINUQMasked256
	OpAMD64VPMINUQMasked512
	OpAMD64VPMINUW128
	OpAMD64VPMINUW256
	OpAMD64VPMINUW512
	OpAMD64VPMINUWMasked128
	OpAMD64VPMINUWMasked256
	OpAMD64VPMINUWMasked512
	OpAMD64VPMOVDB128_128
	OpAMD64VPMOVDB128_256
	OpAMD64VPMOVDB128_512
	OpAMD64VPMOVDBMasked128_128
	OpAMD64VPMOVDBMasked128_256
	OpAMD64VPMOVDBMasked128_512
	OpAMD64VPMOVDW128_128
	OpAMD64VPMOVDW128_256
	OpAMD64VPMOVDW256
	OpAMD64VPMOVDWMasked128_128
	OpAMD64VPMOVDWMasked128_256
	OpAMD64VPMOVDWMasked256
	OpAMD64VPMOVQB128_128
	OpAMD64VPMOVQB128_256
	OpAMD64VPMOVQB128_512
	OpAMD64VPMOVQBMasked128_128
	OpAMD64VPMOVQBMasked128_256
	OpAMD64VPMOVQBMasked128_512
	OpAMD64VPMOVQD128_128
	OpAMD64VPMOVQD128_256
	OpAMD64VPMOVQD256
	OpAMD64VPMOVQDMasked128_128
	OpAMD64VPMOVQDMasked128_256
	OpAMD64VPMOVQDMasked256
	OpAMD64VPMOVQW128_128
	OpAMD64VPMOVQW128_256
	OpAMD64VPMOVQW128_512
	OpAMD64VPMOVQWMasked128_128
	OpAMD64VPMOVQWMasked128_256
	OpAMD64VPMOVQWMasked128_512
	OpAMD64VPMOVSDB128_128
	OpAMD64VPMOVSDB128_256
	OpAMD64VPMOVSDB128_512
	OpAMD64VPMOVSDBMasked128_128
	OpAMD64VPMOVSDBMasked128_256
	OpAMD64VPMOVSDBMasked128_512
	OpAMD64VPMOVSDW128_128
	OpAMD64VPMOVSDW128_256
	OpAMD64VPMOVSDW256
	OpAMD64VPMOVSDWMasked128_128
	OpAMD64VPMOVSDWMasked128_256
	OpAMD64VPMOVSDWMasked256
	OpAMD64VPMOVSQB128_128
	OpAMD64VPMOVSQB128_256
	OpAMD64VPMOVSQB128_512
	OpAMD64VPMOVSQBMasked128_128
	OpAMD64VPMOVSQBMasked128_256
	OpAMD64VPMOVSQBMasked128_512
	OpAMD64VPMOVSQD128_128
	OpAMD64VPMOVSQD128_256
	OpAMD64VPMOVSQD256
	OpAMD64VPMOVSQDMasked128_128
	OpAMD64VPMOVSQDMasked128_256
	OpAMD64VPMOVSQDMasked256
	OpAMD64VPMOVSQW128_128
	OpAMD64VPMOVSQW128_256
	OpAMD64VPMOVSQW128_512
	OpAMD64VPMOVSQWMasked128_128
	OpAMD64VPMOVSQWMasked128_256
	OpAMD64VPMOVSQWMasked128_512
	OpAMD64VPMOVSWB128_128
	OpAMD64VPMOVSWB128_256
	OpAMD64VPMOVSWB256
	OpAMD64VPMOVSWBMasked128_128
	OpAMD64VPMOVSWBMasked128_256
	OpAMD64VPMOVSWBMasked256
	OpAMD64VPMOVSXBD128
	OpAMD64VPMOVSXBD256
	OpAMD64VPMOVSXBD512
	OpAMD64VPMOVSXBDMasked128
	OpAMD64VPMOVSXBDMasked256
	OpAMD64VPMOVSXBDMasked512
	OpAMD64VPMOVSXBQ128
	OpAMD64VPMOVSXBQ256
	OpAMD64VPMOVSXBQ512
	OpAMD64VPMOVSXBQMasked128
	OpAMD64VPMOVSXBQMasked256
	OpAMD64VPMOVSXBQMasked512
	OpAMD64VPMOVSXBW128
	OpAMD64VPMOVSXBW256
	OpAMD64VPMOVSXBW512
	OpAMD64VPMOVSXBWMasked128
	OpAMD64VPMOVSXBWMasked256
	OpAMD64VPMOVSXBWMasked512
	OpAMD64VPMOVSXDQ128
	OpAMD64VPMOVSXDQ256
	OpAMD64VPMOVSXDQ512
	OpAMD64VPMOVSXDQMasked128
	OpAMD64VPMOVSXDQMasked256
	OpAMD64VPMOVSXDQMasked512
	OpAMD64VPMOVSXWD128
	OpAMD64VPMOVSXWD256
	OpAMD64VPMOVSXWD512
	OpAMD64VPMOVSXWDMasked128
	OpAMD64VPMOVSXWDMasked256
	OpAMD64VPMOVSXWDMasked512
	OpAMD64VPMOVSXWQ128
	OpAMD64VPMOVSXWQ256
	OpAMD64VPMOVSXWQ512
	OpAMD64VPMOVSXWQMasked128
	OpAMD64VPMOVSXWQMasked256
	OpAMD64VPMOVSXWQMasked512
	OpAMD64VPMOVUSDB128_128
	OpAMD64VPMOVUSDB128_256
	OpAMD64VPMOVUSDB128_512
	OpAMD64VPMOVUSDBMasked128_128
	OpAMD64VPMOVUSDBMasked128_256
	OpAMD64VPMOVUSDBMasked128_512
	OpAMD64VPMOVUSDW128_128
	OpAMD64VPMOVUSDW128_256
	OpAMD64VPMOVUSDW256
	OpAMD64VPMOVUSDWMasked128_128
	OpAMD64VPMOVUSDWMasked128_256
	OpAMD64VPMOVUSDWMasked256
	OpAMD64VPMOVUSQB128_128
	OpAMD64VPMOVUSQB128_256
	OpAMD64VPMOVUSQB128_512
	OpAMD64VPMOVUSQBMasked128_128
	OpAMD64VPMOVUSQBMasked128_256
	OpAMD64VPMOVUSQBMasked128_512
	OpAMD64VPMOVUSQD128_128
	OpAMD64VPMOVUSQD128_256
	OpAMD64VPMOVUSQD256
	OpAMD64VPMOVUSQDMasked128_128
	OpAMD64VPMOVUSQDMasked128_256
	OpAMD64VPMOVUSQDMasked256
	OpAMD64VPMOVUSQW128_128
	OpAMD64VPMOVUSQW128_256
	OpAMD64VPMOVUSQW128_512
	OpAMD64VPMOVUSQWMasked128_128
	OpAMD64VPMOVUSQWMasked128_256
	OpAMD64VPMOVUSQWMasked128_512
	OpAMD64VPMOVUSWB128_128
	OpAMD64VPMOVUSWB128_256
	OpAMD64VPMOVUSWB256
	OpAMD64VPMOVUSWBMasked128_128
	OpAMD64VPMOVUSWBMasked128_256
	OpAMD64VPMOVUSWBMasked256
	OpAMD64VPMOVWB128_128
	OpAMD64VPMOVWB128_256
	OpAMD64VPMOVWB256
	OpAMD64VPMOVWBMasked128_128
	OpAMD64VPMOVWBMasked128_256
	OpAMD64VPMOVWBMasked256
	OpAMD64VPMOVZXBD128
	OpAMD64VPMOVZXBD256
	OpAMD64VPMOVZXBD512
	OpAMD64VPMOVZXBDMasked128
	OpAMD64VPMOVZXBDMasked256
	OpAMD64VPMOVZXBDMasked512
	OpAMD64VPMOVZXBQ128
	OpAMD64VPMOVZXBQ256
	OpAMD64VPMOVZXBQ512
	OpAMD64VPMOVZXBQMasked128
	OpAMD64VPMOVZXBQMasked256
	OpAMD64VPMOVZXBQMasked512
	OpAMD64VPMOVZXBW128
	OpAMD64VPMOVZXBW256
	OpAMD64VPMOVZXBW512
	OpAMD64VPMOVZXBWMasked128
	OpAMD64VPMOVZXBWMasked256
	OpAMD64VPMOVZXBWMasked512
	OpAMD64VPMOVZXDQ128
	OpAMD64VPMOVZXDQ256
	OpAMD64VPMOVZXDQ512
	OpAMD64VPMOVZXDQMasked128
	OpAMD64VPMOVZXDQMasked256
	OpAMD64VPMOVZXDQMasked512
	OpAMD64VPMOVZXWD128
	OpAMD64VPMOVZXWD256
	OpAMD64VPMOVZXWD512
	OpAMD64VPMOVZXWDMasked128
	OpAMD64VPMOVZXWDMasked256
	OpAMD64VPMOVZXWDMasked512
	OpAMD64VPMOVZXWQ128
	OpAMD64VPMOVZXWQ256
	OpAMD64VPMOVZXWQ512
	OpAMD64VPMOVZXWQMasked128
	OpAMD64VPMOVZXWQMasked256
	OpAMD64VPMOVZXWQMasked512
	OpAMD64VPMULDQ128
	OpAMD64VPMULDQ256
	OpAMD64VPMULHUW128
	OpAMD64VPMULHUW256
	OpAMD64VPMULHUW512
	OpAMD64VPMULHUWMasked128
	OpAMD64VPMULHUWMasked256
	OpAMD64VPMULHUWMasked512
	OpAMD64VPMULHW128
	OpAMD64VPMULHW256
	OpAMD64VPMULHW512
	OpAMD64VPMULHWMasked128
	OpAMD64VPMULHWMasked256
	OpAMD64VPMULHWMasked512
	OpAMD64VPMULLD128
	OpAMD64VPMULLD256
	OpAMD64VPMULLD512
	OpAMD64VPMULLDMasked128
	OpAMD64VPMULLDMasked256
	OpAMD64VPMULLDMasked512
	OpAMD64VPMULLQ128
	OpAMD64VPMULLQ256
	OpAMD64VPMULLQ512
	OpAMD64VPMULLQMasked128
	OpAMD64VPMULLQMasked256
	OpAMD64VPMULLQMasked512
	OpAMD64VPMULLW128
	OpAMD64VPMULLW256
	OpAMD64VPMULLW512
	OpAMD64VPMULLWMasked128
	OpAMD64VPMULLWMasked256
	OpAMD64VPMULLWMasked512
	OpAMD64VPMULUDQ128
	OpAMD64VPMULUDQ256
	OpAMD64VPOPCNTB128
	OpAMD64VPOPCNTB256
	OpAMD64VPOPCNTB512
	OpAMD64VPOPCNTBMasked128
	OpAMD64VPOPCNTBMasked256
	OpAMD64VPOPCNTBMasked512
	OpAMD64VPOPCNTD128
	OpAMD64VPOPCNTD256
	OpAMD64VPOPCNTD512
	OpAMD64VPOPCNTDMasked128
	OpAMD64VPOPCNTDMasked256
	OpAMD64VPOPCNTDMasked512
	OpAMD64VPOPCNTQ128
	OpAMD64VPOPCNTQ256
	OpAMD64VPOPCNTQ512
	OpAMD64VPOPCNTQMasked128
	OpAMD64VPOPCNTQMasked256
	OpAMD64VPOPCNTQMasked512
	OpAMD64VPOPCNTW128
	OpAMD64VPOPCNTW256
	OpAMD64VPOPCNTW512
	OpAMD64VPOPCNTWMasked128
	OpAMD64VPOPCNTWMasked256
	OpAMD64VPOPCNTWMasked512
	OpAMD64VPOR128
	OpAMD64VPOR256
	OpAMD64VPORD512
	OpAMD64VPORDMasked128
	OpAMD64VPORDMasked256
	OpAMD64VPORDMasked512
	OpAMD64VPORQ512
	OpAMD64VPORQMasked128
	OpAMD64VPORQMasked256
	OpAMD64VPORQMasked512
	OpAMD64VPROLVD128
	OpAMD64VPROLVD256
	OpAMD64VPROLVD512
	OpAMD64VPROLVDMasked128
	OpAMD64VPROLVDMasked256
	OpAMD64VPROLVDMasked512
	OpAMD64VPROLVQ128
	OpAMD64VPROLVQ256
	OpAMD64VPROLVQ512
	OpAMD64VPROLVQMasked128
	OpAMD64VPROLVQMasked256
	OpAMD64VPROLVQMasked512
	OpAMD64VPRORVD128
	OpAMD64VPRORVD256
	OpAMD64VPRORVD512
	OpAMD64VPRORVDMasked128
	OpAMD64VPRORVDMasked256
	OpAMD64VPRORVDMasked512
	OpAMD64VPRORVQ128
	OpAMD64VPRORVQ256
	OpAMD64VPRORVQ512
	OpAMD64VPRORVQMasked128
	OpAMD64VPRORVQMasked256
	OpAMD64VPRORVQMasked512
	OpAMD64VPSADBW128
	OpAMD64VPSADBW256
	OpAMD64VPSADBW512
	OpAMD64VPSHLDVD128
	OpAMD64VPSHLDVD256
	OpAMD64VPSHLDVD512
	OpAMD64VPSHLDVDMasked128
	OpAMD64VPSHLDVDMasked256
	OpAMD64VPSHLDVDMasked512
	OpAMD64VPSHLDVQ128
	OpAMD64VPSHLDVQ256
	OpAMD64VPSHLDVQ512
	OpAMD64VPSHLDVQMasked128
	OpAMD64VPSHLDVQMasked256
	OpAMD64VPSHLDVQMasked512
	OpAMD64VPSHLDVW128
	OpAMD64VPSHLDVW256
	OpAMD64VPSHLDVW512
	OpAMD64VPSHLDVWMasked128
	OpAMD64VPSHLDVWMasked256
	OpAMD64VPSHLDVWMasked512
	OpAMD64VPSHRDVD128
	OpAMD64VPSHRDVD256
	OpAMD64VPSHRDVD512
	OpAMD64VPSHRDVDMasked128
	OpAMD64VPSHRDVDMasked256
	OpAMD64VPSHRDVDMasked512
	OpAMD64VPSHRDVQ128
	OpAMD64VPSHRDVQ256
	OpAMD64VPSHRDVQ512
	OpAMD64VPSHRDVQMasked128
	OpAMD64VPSHRDVQMasked256
	OpAMD64VPSHRDVQMasked512
	OpAMD64VPSHRDVW128
	OpAMD64VPSHRDVW256
	OpAMD64VPSHRDVW512
	OpAMD64VPSHRDVWMasked128
	OpAMD64VPSHRDVWMasked256
	OpAMD64VPSHRDVWMasked512
	OpAMD64VPSHUFB128
	OpAMD64VPSHUFB256
	OpAMD64VPSHUFB512
	OpAMD64VPSHUFBMasked128
	OpAMD64VPSHUFBMasked256
	OpAMD64VPSHUFBMasked512
	OpAMD64VPSIGNB128
	OpAMD64VPSIGNB256
	OpAMD64VPSIGND128
	OpAMD64VPSIGND256
	OpAMD64VPSIGNW128
	OpAMD64VPSIGNW256
	OpAMD64VPSLLD128
	OpAMD64VPSLLD256
	OpAMD64VPSLLD512
	OpAMD64VPSLLDMasked128
	OpAMD64VPSLLDMasked256
	OpAMD64VPSLLDMasked512
	OpAMD64VPSLLQ128
	OpAMD64VPSLLQ256
	OpAMD64VPSLLQ512
	OpAMD64VPSLLQMasked128
	OpAMD64VPSLLQMasked256
	OpAMD64VPSLLQMasked512
	OpAMD64VPSLLVD128
	OpAMD64VPSLLVD256
	OpAMD64VPSLLVD512
	OpAMD64VPSLLVDMasked128
	OpAMD64VPSLLVDMasked256
	OpAMD64VPSLLVDMasked512
	OpAMD64VPSLLVQ128
	OpAMD64VPSLLVQ256
	OpAMD64VPSLLVQ512
	OpAMD64VPSLLVQMasked128
	OpAMD64VPSLLVQMasked256
	OpAMD64VPSLLVQMasked512
	OpAMD64VPSLLVW128
	OpAMD64VPSLLVW256
	OpAMD64VPSLLVW512
	OpAMD64VPSLLVWMasked128
	OpAMD64VPSLLVWMasked256
	OpAMD64VPSLLVWMasked512
	OpAMD64VPSLLW128
	OpAMD64VPSLLW256
	OpAMD64VPSLLW512
	OpAMD64VPSLLWMasked128
	OpAMD64VPSLLWMasked256
	OpAMD64VPSLLWMasked512
	OpAMD64VPSRAD128
	OpAMD64VPSRAD256
	OpAMD64VPSRAD512
	OpAMD64VPSRADMasked128
	OpAMD64VPSRADMasked256
	OpAMD64VPSRADMasked512
	OpAMD64VPSRAQ128
	OpAMD64VPSRAQ256
	OpAMD64VPSRAQ512
	OpAMD64VPSRAQMasked128
	OpAMD64VPSRAQMasked256
	OpAMD64VPSRAQMasked512
	OpAMD64VPSRAVD128
	OpAMD64VPSRAVD256
	OpAMD64VPSRAVD512
	OpAMD64VPSRAVDMasked128
	OpAMD64VPSRAVDMasked256
	OpAMD64VPSRAVDMasked512
	OpAMD64VPSRAVQ128
	OpAMD64VPSRAVQ256
	OpAMD64VPSRAVQ512
	OpAMD64VPSRAVQMasked128
	OpAMD64VPSRAVQMasked256
	OpAMD64VPSRAVQMasked512
	OpAMD64VPSRAVW128
	OpAMD64VPSRAVW256
	OpAMD64VPSRAVW512
	OpAMD64VPSRAVWMasked128
	OpAMD64VPSRAVWMasked256
	OpAMD64VPSRAVWMasked512
	OpAMD64VPSRAW128
	OpAMD64VPSRAW256
	OpAMD64VPSRAW512
	OpAMD64VPSRAWMasked128
	OpAMD64VPSRAWMasked256
	OpAMD64VPSRAWMasked512
	OpAMD64VPSRLD128
	OpAMD64VPSRLD256
	OpAMD64VPSRLD512
	OpAMD64VPSRLDMasked128
	OpAMD64VPSRLDMasked256
	OpAMD64VPSRLDMasked512
	OpAMD64VPSRLQ128
	OpAMD64VPSRLQ256
	OpAMD64VPSRLQ512
	OpAMD64VPSRLQMasked128
	OpAMD64VPSRLQMasked256
	OpAMD64VPSRLQMasked512
	OpAMD64VPSRLVD128
	OpAMD64VPSRLVD256
	OpAMD64VPSRLVD512
	OpAMD64VPSRLVDMasked128
	OpAMD64VPSRLVDMasked256
	OpAMD64VPSRLVDMasked512
	OpAMD64VPSRLVQ128
	OpAMD64VPSRLVQ256
	OpAMD64VPSRLVQ512
	OpAMD64VPSRLVQMasked128
	OpAMD64VPSRLVQMasked256
	OpAMD64VPSRLVQMasked512
	OpAMD64VPSRLVW128
	OpAMD64VPSRLVW256
	OpAMD64VPSRLVW512
	OpAMD64VPSRLVWMasked128
	OpAMD64VPSRLVWMasked256
	OpAMD64VPSRLVWMasked512
	OpAMD64VPSRLW128
	OpAMD64VPSRLW256
	OpAMD64VPSRLW512
	OpAMD64VPSRLWMasked128
	OpAMD64VPSRLWMasked256
	OpAMD64VPSRLWMasked512
	OpAMD64VPSUBB128
	OpAMD64VPSUBB256
	OpAMD64VPSUBB512
	OpAMD64VPSUBBMasked128
	OpAMD64VPSUBBMasked256
	OpAMD64VPSUBBMasked512
	OpAMD64VPSUBD128
	OpAMD64VPSUBD256
	OpAMD64VPSUBD512
	OpAMD64VPSUBDMasked128
	OpAMD64VPSUBDMasked256
	OpAMD64VPSUBDMasked512
	OpAMD64VPSUBQ128
	OpAMD64VPSUBQ256
	OpAMD64VPSUBQ512
	OpAMD64VPSUBQMasked128
	OpAMD64VPSUBQMasked256
	OpAMD64VPSUBQMasked512
	OpAMD64VPSUBSB128
	OpAMD64VPSUBSB256
	OpAMD64VPSUBSB512
	OpAMD64VPSUBSBMasked128
	OpAMD64VPSUBSBMasked256
	OpAMD64VPSUBSBMasked512
	OpAMD64VPSUBSW128
	OpAMD64VPSUBSW256
	OpAMD64VPSUBSW512
	OpAMD64VPSUBSWMasked128
	OpAMD64VPSUBSWMasked256
	OpAMD64VPSUBSWMasked512
	OpAMD64VPSUBUSB128
	OpAMD64VPSUBUSB256
	OpAMD64VPSUBUSB512
	OpAMD64VPSUBUSBMasked128
	OpAMD64VPSUBUSBMasked256
	OpAMD64VPSUBUSBMasked512
	OpAMD64VPSUBUSW128
	OpAMD64VPSUBUSW256
	OpAMD64VPSUBUSW512
	OpAMD64VPSUBUSWMasked128
	OpAMD64VPSUBUSWMasked256
	OpAMD64VPSUBUSWMasked512
	OpAMD64VPSUBW128
	OpAMD64VPSUBW256
	OpAMD64VPSUBW512
	OpAMD64VPSUBWMasked128
	OpAMD64VPSUBWMasked256
	OpAMD64VPSUBWMasked512
	OpAMD64VPUNPCKHDQ128
	OpAMD64VPUNPCKHDQ256
	OpAMD64VPUNPCKHDQ512
	OpAMD64VPUNPCKHQDQ128
	OpAMD64VPUNPCKHQDQ256
	OpAMD64VPUNPCKHQDQ512
	OpAMD64VPUNPCKHWD128
	OpAMD64VPUNPCKHWD256
	OpAMD64VPUNPCKHWD512
	OpAMD64VPUNPCKLDQ128
	OpAMD64VPUNPCKLDQ256
	OpAMD64VPUNPCKLDQ512
	OpAMD64VPUNPCKLQDQ128
	OpAMD64VPUNPCKLQDQ256
	OpAMD64VPUNPCKLQDQ512
	OpAMD64VPUNPCKLWD128
	OpAMD64VPUNPCKLWD256
	OpAMD64VPUNPCKLWD512
	OpAMD64VPXOR128
	OpAMD64VPXOR256
	OpAMD64VPXORD512
	OpAMD64VPXORDMasked128
	OpAMD64VPXORDMasked256
	OpAMD64VPXORDMasked512
	OpAMD64VPXORQ512
	OpAMD64VPXORQMasked128
	OpAMD64VPXORQMasked256
	OpAMD64VPXORQMasked512
	OpAMD64VRCP14PD128
	OpAMD64VRCP14PD256
	OpAMD64VRCP14PD512
	OpAMD64VRCP14PDMasked128
	OpAMD64VRCP14PDMasked256
	OpAMD64VRCP14PDMasked512
	OpAMD64VRCP14PS512
	OpAMD64VRCP14PSMasked128
	OpAMD64VRCP14PSMasked256
	OpAMD64VRCP14PSMasked512
	OpAMD64VRCPPS128
	OpAMD64VRCPPS256
	OpAMD64VRSQRT14PD128
	OpAMD64VRSQRT14PD256
	OpAMD64VRSQRT14PD512
	OpAMD64VRSQRT14PDMasked128
	OpAMD64VRSQRT14PDMasked256
	OpAMD64VRSQRT14PDMasked512
	OpAMD64VRSQRT14PS512
	OpAMD64VRSQRT14PSMasked128
	OpAMD64VRSQRT14PSMasked256
	OpAMD64VRSQRT14PSMasked512
	OpAMD64VRSQRTPS128
	OpAMD64VRSQRTPS256
	OpAMD64VSCALEFPD128
	OpAMD64VSCALEFPD256
	OpAMD64VSCALEFPD512
	OpAMD64VSCALEFPDMasked128
	OpAMD64VSCALEFPDMasked256
	OpAMD64VSCALEFPDMasked512
	OpAMD64VSCALEFPS128
	OpAMD64VSCALEFPS256
	OpAMD64VSCALEFPS512
	OpAMD64VSCALEFPSMasked128
	OpAMD64VSCALEFPSMasked256
	OpAMD64VSCALEFPSMasked512
	OpAMD64VSQRTPD128
	OpAMD64VSQRTPD256
	OpAMD64VSQRTPD512
	OpAMD64VSQRTPDMasked128
	OpAMD64VSQRTPDMasked256
	OpAMD64VSQRTPDMasked512
	OpAMD64VSQRTPS128
	OpAMD64VSQRTPS256
	OpAMD64VSQRTPS512
	OpAMD64VSQRTPSMasked128
	OpAMD64VSQRTPSMasked256
	OpAMD64VSQRTPSMasked512
	OpAMD64VSUBPD128
	OpAMD64VSUBPD256
	OpAMD64VSUBPD512
	OpAMD64VSUBPDMasked128
	OpAMD64VSUBPDMasked256
	OpAMD64VSUBPDMasked512
	OpAMD64VSUBPS128
	OpAMD64VSUBPS256
	OpAMD64VSUBPS512
	OpAMD64VSUBPSMasked128
	OpAMD64VSUBPSMasked256
	OpAMD64VSUBPSMasked512
	OpAMD64SHA1RNDS4128
	OpAMD64VAESKEYGENASSIST128
	OpAMD64VCMPPD128
	OpAMD64VCMPPD256
	OpAMD64VCMPPD512
	OpAMD64VCMPPDMasked128
	OpAMD64VCMPPDMasked256
	OpAMD64VCMPPDMasked512
	OpAMD64VCMPPS128
	OpAMD64VCMPPS256
	OpAMD64VCMPPS512
	OpAMD64VCMPPSMasked128
	OpAMD64VCMPPSMasked256
	OpAMD64VCMPPSMasked512
	OpAMD64VEXTRACTF64X4256
	OpAMD64VEXTRACTF128128
	OpAMD64VEXTRACTI64X4256
	OpAMD64VEXTRACTI128128
	OpAMD64VGF2P8AFFINEINVQB128
	OpAMD64VGF2P8AFFINEINVQB256
	OpAMD64VGF2P8AFFINEINVQB512
	OpAMD64VGF2P8AFFINEINVQBMasked128
	OpAMD64VGF2P8AFFINEINVQBMasked256
	OpAMD64VGF2P8AFFINEINVQBMasked512
	OpAMD64VGF2P8AFFINEQB128
	OpAMD64VGF2P8AFFINEQB256
	OpAMD64VGF2P8AFFINEQB512
	OpAMD64VGF2P8AFFINEQBMasked128
	OpAMD64VGF2P8AFFINEQBMasked256
	OpAMD64VGF2P8AFFINEQBMasked512
	OpAMD64VINSERTF64X4512
	OpAMD64VINSERTF128256
	OpAMD64VINSERTI64X4512
	OpAMD64VINSERTI128256
	OpAMD64VPALIGNR128
	OpAMD64VPALIGNR256
	OpAMD64VPALIGNR512
	OpAMD64VPALIGNRMasked128
	OpAMD64VPALIGNRMasked256
	OpAMD64VPALIGNRMasked512
	OpAMD64VPCLMULQDQ128
	OpAMD64VPCLMULQDQ256
	OpAMD64VPCLMULQDQ512
	OpAMD64VPCMPB512
	OpAMD64VPCMPBMasked128
	OpAMD64VPCMPBMasked256
	OpAMD64VPCMPBMasked512
	OpAMD64VPCMPD512
	OpAMD64VPCMPDMasked128
	OpAMD64VPCMPDMasked256
	OpAMD64VPCMPDMasked512
	OpAMD64VPCMPQ512
	OpAMD64VPCMPQMasked128
	OpAMD64VPCMPQMasked256
	OpAMD64VPCMPQMasked512
	OpAMD64VPCMPUB512
	OpAMD64VPCMPUBMasked128
	OpAMD64VPCMPUBMasked256
	OpAMD64VPCMPUBMasked512
	OpAMD64VPCMPUD512
	OpAMD64VPCMPUDMasked128
	OpAMD64VPCMPUDMasked256
	OpAMD64VPCMPUDMasked512
	OpAMD64VPCMPUQ512
	OpAMD64VPCMPUQMasked128
	OpAMD64VPCMPUQMasked256
	OpAMD64VPCMPUQMasked512
	OpAMD64VPCMPUW512
	OpAMD64VPCMPUWMasked128
	OpAMD64VPCMPUWMasked256
	OpAMD64VPCMPUWMasked512
	OpAMD64VPCMPW512
	OpAMD64VPCMPWMasked128
	OpAMD64VPCMPWMasked256
	OpAMD64VPCMPWMasked512
	OpAMD64VPERM2F128256
	OpAMD64VPERM2I128256
	OpAMD64VPEXTRB128
	OpAMD64VPEXTRD128
	OpAMD64VPEXTRQ128
	OpAMD64VPEXTRW128
	OpAMD64VPINSRB128
	OpAMD64VPINSRD128
	OpAMD64VPINSRQ128
	OpAMD64VPINSRW128
	OpAMD64VPROLD128
	OpAMD64VPROLD256
	OpAMD64VPROLD512
	OpAMD64VPROLDMasked128
	OpAMD64VPROLDMasked256
	OpAMD64VPROLDMasked512
	OpAMD64VPROLQ128
	OpAMD64VPROLQ256
	OpAMD64VPROLQ512
	OpAMD64VPROLQMasked128
	OpAMD64VPROLQMasked256
	OpAMD64VPROLQMasked512
	OpAMD64VPRORD128
	OpAMD64VPRORD256
	OpAMD64VPRORD512
	OpAMD64VPRORDMasked128
	OpAMD64VPRORDMasked256
	OpAMD64VPRORDMasked512
	OpAMD64VPRORQ128
	OpAMD64VPRORQ256
	OpAMD64VPRORQ512
	OpAMD64VPRORQMasked128
	OpAMD64VPRORQMasked256
	OpAMD64VPRORQMasked512
	OpAMD64VPSHLDD128
	OpAMD64VPSHLDD256
	OpAMD64VPSHLDD512
	OpAMD64VPSHLDDMasked128
	OpAMD64VPSHLDDMasked256
	OpAMD64VPSHLDDMasked512
	OpAMD64VPSHLDQ128
	OpAMD64VPSHLDQ256
	OpAMD64VPSHLDQ512
	OpAMD64VPSHLDQMasked128
	OpAMD64VPSHLDQMasked256
	OpAMD64VPSHLDQMasked512
	OpAMD64VPSHLDW128
	OpAMD64VPSHLDW256
	OpAMD64VPSHLDW512
	OpAMD64VPSHLDWMasked128
	OpAMD64VPSHLDWMasked256
	OpAMD64VPSHLDWMasked512
	OpAMD64VPSHRDD128
	OpAMD64VPSHRDD256
	OpAMD64VPSHRDD512
	OpAMD64VPSHRDDMasked128
	OpAMD64VPSHRDDMasked256
	OpAMD64VPSHRDDMasked512
	OpAMD64VPSHRDQ128
	OpAMD64VPSHRDQ256
	OpAMD64VPSHRDQ512
	OpAMD64VPSHRDQMasked128
	OpAMD64VPSHRDQMasked256
	OpAMD64VPSHRDQMasked512
	OpAMD64VPSHRDW128
	OpAMD64VPSHRDW256
	OpAMD64VPSHRDW512
	OpAMD64VPSHRDWMasked128
	OpAMD64VPSHRDWMasked256
	OpAMD64VPSHRDWMasked512
	OpAMD64VPSHUFD128
	OpAMD64VPSHUFD256
	OpAMD64VPSHUFD512
	OpAMD64VPSHUFDMasked128
	OpAMD64VPSHUFDMasked256
	OpAMD64VPSHUFDMasked512
	OpAMD64VPSHUFHW128
	OpAMD64VPSHUFHW256
	OpAMD64VPSHUFHW512
	OpAMD64VPSHUFHWMasked128
	OpAMD64VPSHUFHWMasked256
	OpAMD64VPSHUFHWMasked512
	OpAMD64VPSHUFLW128
	OpAMD64VPSHUFLW256
	OpAMD64VPSHUFLW512
	OpAMD64VPSHUFLWMasked128
	OpAMD64VPSHUFLWMasked256
	OpAMD64VPSHUFLWMasked512
	OpAMD64VPSLLD128const
	OpAMD64VPSLLD256const
	OpAMD64VPSLLD512const
	OpAMD64VPSLLDMasked128const
	OpAMD64VPSLLDMasked256const
	OpAMD64VPSLLDMasked512const
	OpAMD64VPSLLQ128const
	OpAMD64VPSLLQ256const
	OpAMD64VPSLLQ512const
	OpAMD64VPSLLQMasked128const
	OpAMD64VPSLLQMasked256const
	OpAMD64VPSLLQMasked512const
	OpAMD64VPSLLW128const
	OpAMD64VPSLLW256const
	OpAMD64VPSLLW512const
	OpAMD64VPSLLWMasked128const
	OpAMD64VPSLLWMasked256const
	OpAMD64VPSLLWMasked512const
	OpAMD64VPSRAD128const
	OpAMD64VPSRAD256const
	OpAMD64VPSRAD512const
	OpAMD64VPSRADMasked128const
	OpAMD64VPSRADMasked256const
	OpAMD64VPSRADMasked512const
	OpAMD64VPSRAQ128const
	OpAMD64VPSRAQ256const
	OpAMD64VPSRAQ512const
	OpAMD64VPSRAQMasked128const
	OpAMD64VPSRAQMasked256const
	OpAMD64VPSRAQMasked512const
	OpAMD64VPSRAW128const
	OpAMD64VPSRAW256const
	OpAMD64VPSRAW512const
	OpAMD64VPSRAWMasked128const
	OpAMD64VPSRAWMasked256const
	OpAMD64VPSRAWMasked512const
	OpAMD64VPSRLD128const
	OpAMD64VPSRLD256const
	OpAMD64VPSRLD512const
	OpAMD64VPSRLDMasked128const
	OpAMD64VPSRLDMasked256const
	OpAMD64VPSRLDMasked512const
	OpAMD64VPSRLQ128const
	OpAMD64VPSRLQ256const
	OpAMD64VPSRLQ512const
	OpAMD64VPSRLQMasked128const
	OpAMD64VPSRLQMasked256const
	OpAMD64VPSRLQMasked512const
	OpAMD64VPSRLW128const
	OpAMD64VPSRLW256const
	OpAMD64VPSRLW512const
	OpAMD64VPSRLWMasked128const
	OpAMD64VPSRLWMasked256const
	OpAMD64VPSRLWMasked512const
	OpAMD64VPTERNLOGD128
	OpAMD64VPTERNLOGD256
	OpAMD64VPTERNLOGD512
	OpAMD64VPTERNLOGQ128
	OpAMD64VPTERNLOGQ256
	OpAMD64VPTERNLOGQ512
	OpAMD64VREDUCEPD128
	OpAMD64VREDUCEPD256
	OpAMD64VREDUCEPD512
	OpAMD64VREDUCEPDMasked128
	OpAMD64VREDUCEPDMasked256
	OpAMD64VREDUCEPDMasked512
	OpAMD64VREDUCEPS128
	OpAMD64VREDUCEPS256
	OpAMD64VREDUCEPS512
	OpAMD64VREDUCEPSMasked128
	OpAMD64VREDUCEPSMasked256
	OpAMD64VREDUCEPSMasked512
	OpAMD64VRNDSCALEPD128
	OpAMD64VRNDSCALEPD256
	OpAMD64VRNDSCALEPD512
	OpAMD64VRNDSCALEPDMasked128
	OpAMD64VRNDSCALEPDMasked256
	OpAMD64VRNDSCALEPDMasked512
	OpAMD64VRNDSCALEPS128
	OpAMD64VRNDSCALEPS256
	OpAMD64VRNDSCALEPS512
	OpAMD64VRNDSCALEPSMasked128
	OpAMD64VRNDSCALEPSMasked256
	OpAMD64VRNDSCALEPSMasked512
	OpAMD64VROUNDPD128
	OpAMD64VROUNDPD256
	OpAMD64VROUNDPS128
	OpAMD64VROUNDPS256
	OpAMD64VSHUFPD128
	OpAMD64VSHUFPD256
	OpAMD64VSHUFPD512
	OpAMD64VSHUFPS128
	OpAMD64VSHUFPS256
	OpAMD64VSHUFPS512
	OpAMD64VADDPD128load
	OpAMD64VADDPD256load
	OpAMD64VADDPD512load
	OpAMD64VADDPDMasked128load
	OpAMD64VADDPDMasked256load
	OpAMD64VADDPDMasked512load
	OpAMD64VADDPS128load
	OpAMD64VADDPS256load
	OpAMD64VADDPS512load
	OpAMD64VADDPSMasked128load
	OpAMD64VADDPSMasked256load
	OpAMD64VADDPSMasked512load
	OpAMD64VADDSUBPD128load
	OpAMD64VADDSUBPD256load
	OpAMD64VADDSUBPS128load
	OpAMD64VADDSUBPS256load
	OpAMD64VAESDEC128load
	OpAMD64VAESDEC256load
	OpAMD64VAESDECLAST128load
	OpAMD64VAESDECLAST256load
	OpAMD64VAESENC128load
	OpAMD64VAESENC256load
	OpAMD64VAESENCLAST128load
	OpAMD64VAESENCLAST256load
	OpAMD64VAESIMC128load
	OpAMD64VBROADCASTSD256load
	OpAMD64VBROADCASTSD512load
	OpAMD64VBROADCASTSDMasked256load
	OpAMD64VBROADCASTSDMasked512load
	OpAMD64VBROADCASTSS128load
	OpAMD64VBROADCASTSS256load
	OpAMD64VBROADCASTSS512load
	OpAMD64VBROADCASTSSMasked128load
	OpAMD64VBROADCASTSSMasked256load
	OpAMD64VBROADCASTSSMasked512load
	OpAMD64VCVTDQ2PD256load
	OpAMD64VCVTDQ2PD512load
	OpAMD64VCVTDQ2PDMasked256load
	OpAMD64VCVTDQ2PDMasked512load
	OpAMD64VCVTDQ2PS128load
	OpAMD64VCVTDQ2PS256load
	OpAMD64VCVTDQ2PS512load
	OpAMD64VCVTDQ2PSMasked128load
	OpAMD64VCVTDQ2PSMasked256load
	OpAMD64VCVTDQ2PSMasked512load
	OpAMD64VCVTPD2PS256load
	OpAMD64VCVTPD2PSMasked256load
	OpAMD64VCVTPD2PSX128load
	OpAMD64VCVTPD2PSXMasked128load
	OpAMD64VCVTPD2PSY128load
	OpAMD64VCVTPD2PSYMasked128load
	OpAMD64VCVTPS2PD256load
	OpAMD64VCVTPS2PD512load
	OpAMD64VCVTPS2PDMasked256load
	OpAMD64VCVTPS2PDMasked512load
	OpAMD64VCVTQQ2PD128load
	OpAMD64VCVTQQ2PD256load
	OpAMD64VCVTQQ2PD512load
	OpAMD64VCVTQQ2PDMasked128load
	OpAMD64VCVTQQ2PDMasked256load
	OpAMD64VCVTQQ2PDMasked512load
	OpAMD64VCVTQQ2PS256load
	OpAMD64VCVTQQ2PSMasked256load
	OpAMD64VCVTQQ2PSX128load
	OpAMD64VCVTQQ2PSXMasked128load
	OpAMD64VCVTQQ2PSY128load
	OpAMD64VCVTQQ2PSYMasked128load
	OpAMD64VCVTTPD2DQ256load
	OpAMD64VCVTTPD2DQMasked256load
	OpAMD64VCVTTPD2DQX128load
	OpAMD64VCVTTPD2DQXMasked128load
	OpAMD64VCVTTPD2DQY128load
	OpAMD64VCVTTPD2DQYMasked128load
	OpAMD64VCVTTPD2QQ128load
	OpAMD64VCVTTPD2QQ256load
	OpAMD64VCVTTPD2QQ512load
	OpAMD64VCVTTPD2QQMasked128load
	OpAMD64VCVTTPD2QQMasked256load
	OpAMD64VCVTTPD2QQMasked512load
	OpAMD64VCVTTPD2UDQ256load
	OpAMD64VCVTTPD2UDQMasked256load
	OpAMD64VCVTTPD2UDQX128load
	OpAMD64VCVTTPD2UDQXMasked128load
	OpAMD64VCVTTPD2UDQY128load
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	OpAMD64VPROLVQ512load
	OpAMD64VPROLVQMasked128load
	OpAMD64VPROLVQMasked256load
	OpAMD64VPROLVQMasked512load
	OpAMD64VPRORVD128load
	OpAMD64VPRORVD256load
	OpAMD64VPRORVD512load
	OpAMD64VPRORVDMasked128load
	OpAMD64VPRORVDMasked256load
	OpAMD64VPRORVDMasked512load
	OpAMD64VPRORVQ128load
	OpAMD64VPRORVQ256load
	OpAMD64VPRORVQ512load
	OpAMD64VPRORVQMasked128load
	OpAMD64VPRORVQMasked256load
	OpAMD64VPRORVQMasked512load
	OpAMD64VPSADBW128load
	OpAMD64VPSADBW256load
	OpAMD64VPSHLDVD128load
	OpAMD64VPSHLDVD256load
	OpAMD64VPSHLDVD512load
	OpAMD64VPSHLDVDMasked128load
	OpAMD64VPSHLDVDMasked256load
	OpAMD64VPSHLDVDMasked512load
	OpAMD64VPSHLDVQ128load
	OpAMD64VPSHLDVQ256load
	OpAMD64VPSHLDVQ512load
	OpAMD64VPSHLDVQMasked128load
	OpAMD64VPSHLDVQMasked256load
	OpAMD64VPSHLDVQMasked512load
	OpAMD64VPSHLDVW128load
	OpAMD64VPSHLDVW256load
	OpAMD64VPSHLDVWMasked128load
	OpAMD64VPSHLDVWMasked256load
	OpAMD64VPSHRDVD128load
	OpAMD64VPSHRDVD256load
	OpAMD64VPSHRDVD512load
	OpAMD64VPSHRDVDMasked128load
	OpAMD64VPSHRDVDMasked256load
	OpAMD64VPSHRDVDMasked512load
	OpAMD64VPSHRDVQ128load
	OpAMD64VPSHRDVQ256load
	OpAMD64VPSHRDVQ512load
	OpAMD64VPSHRDVQMasked128load
	OpAMD64VPSHRDVQMasked256load
	OpAMD64VPSHRDVQMasked512load
	OpAMD64VPSHRDVW128load
	OpAMD64VPSHRDVW256load
	OpAMD64VPSHRDVWMasked128load
	OpAMD64VPSHRDVWMasked256load
	OpAMD64VPSHUFB128load
	OpAMD64VPSHUFB256load
	OpAMD64VPSHUFBMasked128load
	OpAMD64VPSHUFBMasked256load
	OpAMD64VPSIGNB128load
	OpAMD64VPSIGNB256load
	OpAMD64VPSIGND128load
	OpAMD64VPSIGND256load
	OpAMD64VPSIGNW128load
	OpAMD64VPSIGNW256load
	OpAMD64VPSLLVD128load
	OpAMD64VPSLLVD256load
	OpAMD64VPSLLVD512load
	OpAMD64VPSLLVDMasked128load
	OpAMD64VPSLLVDMasked256load
	OpAMD64VPSLLVDMasked512load
	OpAMD64VPSLLVQ128load
	OpAMD64VPSLLVQ256load
	OpAMD64VPSLLVQ512load
	OpAMD64VPSLLVQMasked128load
	OpAMD64VPSLLVQMasked256load
	OpAMD64VPSLLVQMasked512load
	OpAMD64VPSLLVW128load
	OpAMD64VPSLLVW256load
	OpAMD64VPSLLVWMasked128load
	OpAMD64VPSLLVWMasked256load
	OpAMD64VPSRAVD128load
	OpAMD64VPSRAVD256load
	OpAMD64VPSRAVD512load
	OpAMD64VPSRAVDMasked128load
	OpAMD64VPSRAVDMasked256load
	OpAMD64VPSRAVDMasked512load
	OpAMD64VPSRAVQ128load
	OpAMD64VPSRAVQ256load
	OpAMD64VPSRAVQ512load
	OpAMD64VPSRAVQMasked128load
	OpAMD64VPSRAVQMasked256load
	OpAMD64VPSRAVQMasked512load
	OpAMD64VPSRAVW128load
	OpAMD64VPSRAVW256load
	OpAMD64VPSRAVWMasked128load
	OpAMD64VPSRAVWMasked256load
	OpAMD64VPSRLVD128load
	OpAMD64VPSRLVD256load
	OpAMD64VPSRLVD512load
	OpAMD64VPSRLVDMasked128load
	OpAMD64VPSRLVDMasked256load
	OpAMD64VPSRLVDMasked512load
	OpAMD64VPSRLVQ128load
	OpAMD64VPSRLVQ256load
	OpAMD64VPSRLVQ512load
	OpAMD64VPSRLVQMasked128load
	OpAMD64VPSRLVQMasked256load
	OpAMD64VPSRLVQMasked512load
	OpAMD64VPSRLVW128load
	OpAMD64VPSRLVW256load
	OpAMD64VPSRLVWMasked128load
	OpAMD64VPSRLVWMasked256load
	OpAMD64VPSUBB128load
	OpAMD64VPSUBB256load
	OpAMD64VPSUBBMasked128load
	OpAMD64VPSUBBMasked256load
	OpAMD64VPSUBD128load
	OpAMD64VPSUBD256load
	OpAMD64VPSUBD512load
	OpAMD64VPSUBDMasked128load
	OpAMD64VPSUBDMasked256load
	OpAMD64VPSUBDMasked512load
	OpAMD64VPSUBQ128load
	OpAMD64VPSUBQ256load
	OpAMD64VPSUBQ512load
	OpAMD64VPSUBQMasked128load
	OpAMD64VPSUBQMasked256load
	OpAMD64VPSUBQMasked512load
	OpAMD64VPSUBSB128load
	OpAMD64VPSUBSB256load
	OpAMD64VPSUBSBMasked128load
	OpAMD64VPSUBSBMasked256load
	OpAMD64VPSUBSW128load
	OpAMD64VPSUBSW256load
	OpAMD64VPSUBSWMasked128load
	OpAMD64VPSUBSWMasked256load
	OpAMD64VPSUBUSB128load
	OpAMD64VPSUBUSB256load
	OpAMD64VPSUBUSBMasked128load
	OpAMD64VPSUBUSBMasked256load
	OpAMD64VPSUBUSW128load
	OpAMD64VPSUBUSW256load
	OpAMD64VPSUBUSWMasked128load
	OpAMD64VPSUBUSWMasked256load
	OpAMD64VPSUBW128load
	OpAMD64VPSUBW256load
	OpAMD64VPSUBWMasked128load
	OpAMD64VPSUBWMasked256load
	OpAMD64VPUNPCKHDQ128load
	OpAMD64VPUNPCKHDQ256load
	OpAMD64VPUNPCKHDQ512load
	OpAMD64VPUNPCKHQDQ128load
	OpAMD64VPUNPCKHQDQ256load
	OpAMD64VPUNPCKHQDQ512load
	OpAMD64VPUNPCKHWD128load
	OpAMD64VPUNPCKHWD256load
	OpAMD64VPUNPCKLDQ128load
	OpAMD64VPUNPCKLDQ256load
	OpAMD64VPUNPCKLDQ512load
	OpAMD64VPUNPCKLQDQ128load
	OpAMD64VPUNPCKLQDQ256load
	OpAMD64VPUNPCKLQDQ512load
	OpAMD64VPUNPCKLWD128load
	OpAMD64VPUNPCKLWD256load
	OpAMD64VPXOR128load
	OpAMD64VPXOR256load
	OpAMD64VPXORD512load
	OpAMD64VPXORDMasked128load
	OpAMD64VPXORDMasked256load
	OpAMD64VPXORDMasked512load
	OpAMD64VPXORQ512load
	OpAMD64VPXORQMasked128load
	OpAMD64VPXORQMasked256load
	OpAMD64VPXORQMasked512load
	OpAMD64VRCP14PD128load
	OpAMD64VRCP14PD256load
	OpAMD64VRCP14PD512load
	OpAMD64VRCP14PDMasked128load
	OpAMD64VRCP14PDMasked256load
	OpAMD64VRCP14PDMasked512load
	OpAMD64VRCP14PS512load
	OpAMD64VRCP14PSMasked128load
	OpAMD64VRCP14PSMasked256load
	OpAMD64VRCP14PSMasked512load
	OpAMD64VRCPPS128load
	OpAMD64VRCPPS256load
	OpAMD64VRSQRT14PD128load
	OpAMD64VRSQRT14PD256load
	OpAMD64VRSQRT14PD512load
	OpAMD64VRSQRT14PDMasked128load
	OpAMD64VRSQRT14PDMasked256load
	OpAMD64VRSQRT14PDMasked512load
	OpAMD64VRSQRT14PS512load
	OpAMD64VRSQRT14PSMasked128load
	OpAMD64VRSQRT14PSMasked256load
	OpAMD64VRSQRT14PSMasked512load
	OpAMD64VRSQRTPS128load
	OpAMD64VRSQRTPS256load
	OpAMD64VSCALEFPD128load
	OpAMD64VSCALEFPD256load
	OpAMD64VSCALEFPD512load
	OpAMD64VSCALEFPDMasked128load
	OpAMD64VSCALEFPDMasked256load
	OpAMD64VSCALEFPDMasked512load
	OpAMD64VSCALEFPS128load
	OpAMD64VSCALEFPS256load
	OpAMD64VSCALEFPS512load
	OpAMD64VSCALEFPSMasked128load
	OpAMD64VSCALEFPSMasked256load
	OpAMD64VSCALEFPSMasked512load
	OpAMD64VSQRTPD128load
	OpAMD64VSQRTPD256load
	OpAMD64VSQRTPD512load
	OpAMD64VSQRTPDMasked128load
	OpAMD64VSQRTPDMasked256load
	OpAMD64VSQRTPDMasked512load
	OpAMD64VSQRTPS128load
	OpAMD64VSQRTPS256load
	OpAMD64VSQRTPS512load
	OpAMD64VSQRTPSMasked128load
	OpAMD64VSQRTPSMasked256load
	OpAMD64VSQRTPSMasked512load
	OpAMD64VSUBPD128load
	OpAMD64VSUBPD256load
	OpAMD64VSUBPD512load
	OpAMD64VSUBPDMasked128load
	OpAMD64VSUBPDMasked256load
	OpAMD64VSUBPDMasked512load
	OpAMD64VSUBPS128load
	OpAMD64VSUBPS256load
	OpAMD64VSUBPS512load
	OpAMD64VSUBPSMasked128load
	OpAMD64VSUBPSMasked256load
	OpAMD64VSUBPSMasked512load
	OpAMD64VAESKEYGENASSIST128load
	OpAMD64VCMPPD128load
	OpAMD64VCMPPD256load
	OpAMD64VCMPPD512load
	OpAMD64VCMPPDMasked128load
	OpAMD64VCMPPDMasked256load
	OpAMD64VCMPPDMasked512load
	OpAMD64VCMPPS128load
	OpAMD64VCMPPS256load
	OpAMD64VCMPPS512load
	OpAMD64VCMPPSMasked128load
	OpAMD64VCMPPSMasked256load
	OpAMD64VCMPPSMasked512load
	OpAMD64VGF2P8AFFINEINVQB128load
	OpAMD64VGF2P8AFFINEINVQB256load
	OpAMD64VGF2P8AFFINEINVQB512load
	OpAMD64VGF2P8AFFINEINVQBMasked128load
	OpAMD64VGF2P8AFFINEINVQBMasked256load
	OpAMD64VGF2P8AFFINEINVQBMasked512load
	OpAMD64VGF2P8AFFINEQB128load
	OpAMD64VGF2P8AFFINEQB256load
	OpAMD64VGF2P8AFFINEQB512load
	OpAMD64VGF2P8AFFINEQBMasked128load
	OpAMD64VGF2P8AFFINEQBMasked256load
	OpAMD64VGF2P8AFFINEQBMasked512load
	OpAMD64VINSERTF64X4512load
	OpAMD64VINSERTF128256load
	OpAMD64VINSERTI64X4512load
	OpAMD64VINSERTI128256load
	OpAMD64VPALIGNR128load
	OpAMD64VPALIGNR256load
	OpAMD64VPALIGNRMasked128load
	OpAMD64VPALIGNRMasked256load
	OpAMD64VPCLMULQDQ128load
	OpAMD64VPCLMULQDQ256load
	OpAMD64VPCMPBMasked128load
	OpAMD64VPCMPBMasked256load
	OpAMD64VPCMPD512load
	OpAMD64VPCMPDMasked128load
	OpAMD64VPCMPDMasked256load
	OpAMD64VPCMPDMasked512load
	OpAMD64VPCMPQ512load
	OpAMD64VPCMPQMasked128load
	OpAMD64VPCMPQMasked256load
	OpAMD64VPCMPQMasked512load
	OpAMD64VPCMPUBMasked128load
	OpAMD64VPCMPUBMasked256load
	OpAMD64VPCMPUD512load
	OpAMD64VPCMPUDMasked128load
	OpAMD64VPCMPUDMasked256load
	OpAMD64VPCMPUDMasked512load
	OpAMD64VPCMPUQ512load
	OpAMD64VPCMPUQMasked128load
	OpAMD64VPCMPUQMasked256load
	OpAMD64VPCMPUQMasked512load
	OpAMD64VPCMPUWMasked128load
	OpAMD64VPCMPUWMasked256load
	OpAMD64VPCMPWMasked128load
	OpAMD64VPCMPWMasked256load
	OpAMD64VPERM2F128256load
	OpAMD64VPERM2I128256load
	OpAMD64VPROLD128load
	OpAMD64VPROLD256load
	OpAMD64VPROLD512load
	OpAMD64VPROLDMasked128load
	OpAMD64VPROLDMasked256load
	OpAMD64VPROLDMasked512load
	OpAMD64VPROLQ128load
	OpAMD64VPROLQ256load
	OpAMD64VPROLQ512load
	OpAMD64VPROLQMasked128load
	OpAMD64VPROLQMasked256load
	OpAMD64VPROLQMasked512load
	OpAMD64VPRORD128load
	OpAMD64VPRORD256load
	OpAMD64VPRORD512load
	OpAMD64VPRORDMasked128load
	OpAMD64VPRORDMasked256load
	OpAMD64VPRORDMasked512load
	OpAMD64VPRORQ128load
	OpAMD64VPRORQ256load
	OpAMD64VPRORQ512load
	OpAMD64VPRORQMasked128load
	OpAMD64VPRORQMasked256load
	OpAMD64VPRORQMasked512load
	OpAMD64VPSHLDD128load
	OpAMD64VPSHLDD256load
	OpAMD64VPSHLDD512load
	OpAMD64VPSHLDDMasked128load
	OpAMD64VPSHLDDMasked256load
	OpAMD64VPSHLDDMasked512load
	OpAMD64VPSHLDQ128load
	OpAMD64VPSHLDQ256load
	OpAMD64VPSHLDQ512load
	OpAMD64VPSHLDQMasked128load
	OpAMD64VPSHLDQMasked256load
	OpAMD64VPSHLDQMasked512load
	OpAMD64VPSHLDW128load
	OpAMD64VPSHLDW256load
	OpAMD64VPSHLDWMasked128load
	OpAMD64VPSHLDWMasked256load
	OpAMD64VPSHRDD128load
	OpAMD64VPSHRDD256load
	OpAMD64VPSHRDD512load
	OpAMD64VPSHRDDMasked128load
	OpAMD64VPSHRDDMasked256load
	OpAMD64VPSHRDDMasked512load
	OpAMD64VPSHRDQ128load
	OpAMD64VPSHRDQ256load
	OpAMD64VPSHRDQ512load
	OpAMD64VPSHRDQMasked128load
	OpAMD64VPSHRDQMasked256load
	OpAMD64VPSHRDQMasked512load
	OpAMD64VPSHRDW128load
	OpAMD64VPSHRDW256load
	OpAMD64VPSHRDWMasked128load
	OpAMD64VPSHRDWMasked256load
	OpAMD64VPSHUFD128load
	OpAMD64VPSHUFD256load
	OpAMD64VPSHUFD512load
	OpAMD64VPSHUFDMasked128load
	OpAMD64VPSHUFDMasked256load
	OpAMD64VPSHUFDMasked512load
	OpAMD64VPSHUFHW128load
	OpAMD64VPSHUFHW256load
	OpAMD64VPSHUFHWMasked128load
	OpAMD64VPSHUFHWMasked256load
	OpAMD64VPSHUFLW128load
	OpAMD64VPSHUFLW256load
	OpAMD64VPSHUFLWMasked128load
	OpAMD64VPSHUFLWMasked256load
	OpAMD64VPSLLD512constload
	OpAMD64VPSLLDMasked128constload
	OpAMD64VPSLLDMasked256constload
	OpAMD64VPSLLDMasked512constload
	OpAMD64VPSLLQ512constload
	OpAMD64VPSLLQMasked128constload
	OpAMD64VPSLLQMasked256constload
	OpAMD64VPSLLQMasked512constload
	OpAMD64VPSLLWMasked128constload
	OpAMD64VPSLLWMasked256constload
	OpAMD64VPSRAD512constload
	OpAMD64VPSRADMasked128constload
	OpAMD64VPSRADMasked256constload
	OpAMD64VPSRADMasked512constload
	OpAMD64VPSRAQ128constload
	OpAMD64VPSRAQ256constload
	OpAMD64VPSRAQ512constload
	OpAMD64VPSRAQMasked128constload
	OpAMD64VPSRAQMasked256constload
	OpAMD64VPSRAQMasked512constload
	OpAMD64VPSRAWMasked128constload
	OpAMD64VPSRAWMasked256constload
	OpAMD64VPSRLD512constload
	OpAMD64VPSRLDMasked128constload
	OpAMD64VPSRLDMasked256constload
	OpAMD64VPSRLDMasked512constload
	OpAMD64VPSRLQ512constload
	OpAMD64VPSRLQMasked128constload
	OpAMD64VPSRLQMasked256constload
	OpAMD64VPSRLQMasked512constload
	OpAMD64VPSRLWMasked128constload
	OpAMD64VPSRLWMasked256constload
	OpAMD64VPTERNLOGD128load
	OpAMD64VPTERNLOGD256load
	OpAMD64VPTERNLOGD512load
	OpAMD64VPTERNLOGQ128load
	OpAMD64VPTERNLOGQ256load
	OpAMD64VPTERNLOGQ512load
	OpAMD64VREDUCEPD128load
	OpAMD64VREDUCEPD256load
	OpAMD64VREDUCEPD512load
	OpAMD64VREDUCEPDMasked128load
	OpAMD64VREDUCEPDMasked256load
	OpAMD64VREDUCEPDMasked512load
	OpAMD64VREDUCEPS128load
	OpAMD64VREDUCEPS256load
	OpAMD64VREDUCEPS512load
	OpAMD64VREDUCEPSMasked128load
	OpAMD64VREDUCEPSMasked256load
	OpAMD64VREDUCEPSMasked512load
	OpAMD64VRNDSCALEPD128load
	OpAMD64VRNDSCALEPD256load
	OpAMD64VRNDSCALEPD512load
	OpAMD64VRNDSCALEPDMasked128load
	OpAMD64VRNDSCALEPDMasked256load
	OpAMD64VRNDSCALEPDMasked512load
	OpAMD64VRNDSCALEPS128load
	OpAMD64VRNDSCALEPS256load
	OpAMD64VRNDSCALEPS512load
	OpAMD64VRNDSCALEPSMasked128load
	OpAMD64VRNDSCALEPSMasked256load
	OpAMD64VRNDSCALEPSMasked512load
	OpAMD64VROUNDPD128load
	OpAMD64VROUNDPD256load
	OpAMD64VROUNDPS128load
	OpAMD64VROUNDPS256load
	OpAMD64VSHUFPD128load
	OpAMD64VSHUFPD256load
	OpAMD64VSHUFPD512load
	OpAMD64VSHUFPS128load
	OpAMD64VSHUFPS256load
	OpAMD64VSHUFPS512load
	OpAMD64VADDPDMasked128Merging
	OpAMD64VADDPDMasked256Merging
	OpAMD64VADDPDMasked512Merging
	OpAMD64VADDPSMasked128Merging
	OpAMD64VADDPSMasked256Merging
	OpAMD64VADDPSMasked512Merging
	OpAMD64VBROADCASTSDMasked256Merging
	OpAMD64VBROADCASTSDMasked512Merging
	OpAMD64VBROADCASTSSMasked128Merging
	OpAMD64VBROADCASTSSMasked256Merging
	OpAMD64VBROADCASTSSMasked512Merging
	OpAMD64VCVTDQ2PDMasked256Merging
	OpAMD64VCVTDQ2PDMasked512Merging
	OpAMD64VCVTDQ2PSMasked128Merging
	OpAMD64VCVTDQ2PSMasked256Merging
	OpAMD64VCVTDQ2PSMasked512Merging
	OpAMD64VCVTPD2PSMasked256Merging
	OpAMD64VCVTPD2PSXMasked128Merging
	OpAMD64VCVTPD2PSYMasked128Merging
	OpAMD64VCVTPS2PDMasked256Merging
	OpAMD64VCVTPS2PDMasked512Merging
	OpAMD64VCVTQQ2PDMasked128Merging
	OpAMD64VCVTQQ2PDMasked256Merging
	OpAMD64VCVTQQ2PDMasked512Merging
	OpAMD64VCVTQQ2PSMasked256Merging
	OpAMD64VCVTQQ2PSXMasked128Merging
	OpAMD64VCVTQQ2PSYMasked128Merging
	OpAMD64VCVTTPD2DQMasked256Merging
	OpAMD64VCVTTPD2DQXMasked128Merging
	OpAMD64VCVTTPD2DQYMasked128Merging
	OpAMD64VCVTTPD2QQMasked128Merging
	OpAMD64VCVTTPD2QQMasked256Merging
	OpAMD64VCVTTPD2QQMasked512Merging
	OpAMD64VCVTTPD2UDQMasked256Merging
	OpAMD64VCVTTPD2UDQXMasked128Merging
	OpAMD64VCVTTPD2UDQYMasked128Merging
	OpAMD64VCVTTPD2UQQMasked128Merging
	OpAMD64VCVTTPD2UQQMasked256Merging
	OpAMD64VCVTTPD2UQQMasked512Merging
	OpAMD64VCVTTPS2DQMasked128Merging
	OpAMD64VCVTTPS2DQMasked256Merging
	OpAMD64VCVTTPS2DQMasked512Merging
	OpAMD64VCVTTPS2QQMasked256Merging
	OpAMD64VCVTTPS2QQMasked512Merging
	OpAMD64VCVTTPS2UDQMasked128Merging
	OpAMD64VCVTTPS2UDQMasked256Merging
	OpAMD64VCVTTPS2UDQMasked512Merging
	OpAMD64VCVTTPS2UQQMasked256Merging
	OpAMD64VCVTTPS2UQQMasked512Merging
	OpAMD64VCVTUDQ2PDMasked256Merging
	OpAMD64VCVTUDQ2PDMasked512Merging
	OpAMD64VCVTUDQ2PSMasked128Merging
	OpAMD64VCVTUDQ2PSMasked256Merging
	OpAMD64VCVTUDQ2PSMasked512Merging
	OpAMD64VCVTUQQ2PDMasked128Merging
	OpAMD64VCVTUQQ2PDMasked256Merging
	OpAMD64VCVTUQQ2PDMasked512Merging
	OpAMD64VCVTUQQ2PSMasked256Merging
	OpAMD64VCVTUQQ2PSXMasked128Merging
	OpAMD64VCVTUQQ2PSYMasked128Merging
	OpAMD64VDIVPDMasked128Merging
	OpAMD64VDIVPDMasked256Merging
	OpAMD64VDIVPDMasked512Merging
	OpAMD64VDIVPSMasked128Merging
	OpAMD64VDIVPSMasked256Merging
	OpAMD64VDIVPSMasked512Merging
	OpAMD64VGF2P8MULBMasked128Merging
	OpAMD64VGF2P8MULBMasked256Merging
	OpAMD64VGF2P8MULBMasked512Merging
	OpAMD64VMAXPDMasked128Merging
	OpAMD64VMAXPDMasked256Merging
	OpAMD64VMAXPDMasked512Merging
	OpAMD64VMAXPSMasked128Merging
	OpAMD64VMAXPSMasked256Merging
	OpAMD64VMAXPSMasked512Merging
	OpAMD64VMINPDMasked128Merging
	OpAMD64VMINPDMasked256Merging
	OpAMD64VMINPDMasked512Merging
	OpAMD64VMINPSMasked128Merging
	OpAMD64VMINPSMasked256Merging
	OpAMD64VMINPSMasked512Merging
	OpAMD64VMULPDMasked128Merging
	OpAMD64VMULPDMasked256Merging
	OpAMD64VMULPDMasked512Merging
	OpAMD64VMULPSMasked128Merging
	OpAMD64VMULPSMasked256Merging
	OpAMD64VMULPSMasked512Merging
	OpAMD64VPABSBMasked128Merging
	OpAMD64VPABSBMasked256Merging
	OpAMD64VPABSBMasked512Merging
	OpAMD64VPABSDMasked128Merging
	OpAMD64VPABSDMasked256Merging
	OpAMD64VPABSDMasked512Merging
	OpAMD64VPABSQMasked128Merging
	OpAMD64VPABSQMasked256Merging
	OpAMD64VPABSQMasked512Merging
	OpAMD64VPABSWMasked128Merging
	OpAMD64VPABSWMasked256Merging
	OpAMD64VPABSWMasked512Merging
	OpAMD64VPACKSSDWMasked128Merging
	OpAMD64VPACKSSDWMasked256Merging
	OpAMD64VPACKSSDWMasked512Merging
	OpAMD64VPACKUSDWMasked128Merging
	OpAMD64VPACKUSDWMasked256Merging
	OpAMD64VPACKUSDWMasked512Merging
	OpAMD64VPADDBMasked128Merging
	OpAMD64VPADDBMasked256Merging
	OpAMD64VPADDBMasked512Merging
	OpAMD64VPADDDMasked128Merging
	OpAMD64VPADDDMasked256Merging
	OpAMD64VPADDDMasked512Merging
	OpAMD64VPADDQMasked128Merging
	OpAMD64VPADDQMasked256Merging
	OpAMD64VPADDQMasked512Merging
	OpAMD64VPADDSBMasked128Merging
	OpAMD64VPADDSBMasked256Merging
	OpAMD64VPADDSBMasked512Merging
	OpAMD64VPADDSWMasked128Merging
	OpAMD64VPADDSWMasked256Merging
	OpAMD64VPADDSWMasked512Merging
	OpAMD64VPADDUSBMasked128Merging
	OpAMD64VPADDUSBMasked256Merging
	OpAMD64VPADDUSBMasked512Merging
	OpAMD64VPADDUSWMasked128Merging
	OpAMD64VPADDUSWMasked256Merging
	OpAMD64VPADDUSWMasked512Merging
	OpAMD64VPADDWMasked128Merging
	OpAMD64VPADDWMasked256Merging
	OpAMD64VPADDWMasked512Merging
	OpAMD64VPANDDMasked128Merging
	OpAMD64VPANDDMasked256Merging
	OpAMD64VPANDDMasked512Merging
	OpAMD64VPANDQMasked128Merging
	OpAMD64VPANDQMasked256Merging
	OpAMD64VPANDQMasked512Merging
	OpAMD64VPAVGBMasked128Merging
	OpAMD64VPAVGBMasked256Merging
	OpAMD64VPAVGBMasked512Merging
	OpAMD64VPAVGWMasked128Merging
	OpAMD64VPAVGWMasked256Merging
	OpAMD64VPAVGWMasked512Merging
	OpAMD64VPBROADCASTBMasked128Merging
	OpAMD64VPBROADCASTBMasked256Merging
	OpAMD64VPBROADCASTBMasked512Merging
	OpAMD64VPBROADCASTDMasked128Merging
	OpAMD64VPBROADCASTDMasked256Merging
	OpAMD64VPBROADCASTDMasked512Merging
	OpAMD64VPBROADCASTQMasked128Merging
	OpAMD64VPBROADCASTQMasked256Merging
	OpAMD64VPBROADCASTQMasked512Merging
	OpAMD64VPBROADCASTWMasked128Merging
	OpAMD64VPBROADCASTWMasked256Merging
	OpAMD64VPBROADCASTWMasked512Merging
	OpAMD64VPLZCNTDMasked128Merging
	OpAMD64VPLZCNTDMasked256Merging
	OpAMD64VPLZCNTDMasked512Merging
	OpAMD64VPLZCNTQMasked128Merging
	OpAMD64VPLZCNTQMasked256Merging
	OpAMD64VPLZCNTQMasked512Merging
	OpAMD64VPMADDUBSWMasked128Merging
	OpAMD64VPMADDUBSWMasked256Merging
	OpAMD64VPMADDUBSWMasked512Merging
	OpAMD64VPMADDWDMasked128Merging
	OpAMD64VPMADDWDMasked256Merging
	OpAMD64VPMADDWDMasked512Merging
	OpAMD64VPMAXSBMasked128Merging
	OpAMD64VPMAXSBMasked256Merging
	OpAMD64VPMAXSBMasked512Merging
	OpAMD64VPMAXSDMasked128Merging
	OpAMD64VPMAXSDMasked256Merging
	OpAMD64VPMAXSDMasked512Merging
	OpAMD64VPMAXSQMasked128Merging
	OpAMD64VPMAXSQMasked256Merging
	OpAMD64VPMAXSQMasked512Merging
	OpAMD64VPMAXSWMasked128Merging
	OpAMD64VPMAXSWMasked256Merging
	OpAMD64VPMAXSWMasked512Merging
	OpAMD64VPMAXUBMasked128Merging
	OpAMD64VPMAXUBMasked256Merging
	OpAMD64VPMAXUBMasked512Merging
	OpAMD64VPMAXUDMasked128Merging
	OpAMD64VPMAXUDMasked256Merging
	OpAMD64VPMAXUDMasked512Merging
	OpAMD64VPMAXUQMasked128Merging
	OpAMD64VPMAXUQMasked256Merging
	OpAMD64VPMAXUQMasked512Merging
	OpAMD64VPMAXUWMasked128Merging
	OpAMD64VPMAXUWMasked256Merging
	OpAMD64VPMAXUWMasked512Merging
	OpAMD64VPMINSBMasked128Merging
	OpAMD64VPMINSBMasked256Merging
	OpAMD64VPMINSBMasked512Merging
	OpAMD64VPMINSDMasked128Merging
	OpAMD64VPMINSDMasked256Merging
	OpAMD64VPMINSDMasked512Merging
	OpAMD64VPMINSQMasked128Merging
	OpAMD64VPMINSQMasked256Merging
	OpAMD64VPMINSQMasked512Merging
	OpAMD64VPMINSWMasked128Merging
	OpAMD64VPMINSWMasked256Merging
	OpAMD64VPMINSWMasked512Merging
	OpAMD64VPMINUBMasked128Merging
	OpAMD64VPMINUBMasked256Merging
	OpAMD64VPMINUBMasked512Merging
	OpAMD64VPMINUDMasked128Merging
	OpAMD64VPMINUDMasked256Merging
	OpAMD64VPMINUDMasked512Merging
	OpAMD64VPMINUQMasked128Merging
	OpAMD64VPMINUQMasked256Merging
	OpAMD64VPMINUQMasked512Merging
	OpAMD64VPMINUWMasked128Merging
	OpAMD64VPMINUWMasked256Merging
	OpAMD64VPMINUWMasked512Merging
	OpAMD64VPMOVDBMasked128_128Merging
	OpAMD64VPMOVDBMasked128_256Merging
	OpAMD64VPMOVDBMasked128_512Merging
	OpAMD64VPMOVDWMasked128_128Merging
	OpAMD64VPMOVDWMasked128_256Merging
	OpAMD64VPMOVDWMasked256Merging
	OpAMD64VPMOVQBMasked128_128Merging
	OpAMD64VPMOVQBMasked128_256Merging
	OpAMD64VPMOVQBMasked128_512Merging
	OpAMD64VPMOVQDMasked128_128Merging
	OpAMD64VPMOVQDMasked128_256Merging
	OpAMD64VPMOVQDMasked256Merging
	OpAMD64VPMOVQWMasked128_128Merging
	OpAMD64VPMOVQWMasked128_256Merging
	OpAMD64VPMOVQWMasked128_512Merging
	OpAMD64VPMOVSDBMasked128_128Merging
	OpAMD64VPMOVSDBMasked128_256Merging
	OpAMD64VPMOVSDBMasked128_512Merging
	OpAMD64VPMOVSDWMasked128_128Merging
	OpAMD64VPMOVSDWMasked128_256Merging
	OpAMD64VPMOVSDWMasked256Merging
	OpAMD64VPMOVSQBMasked128_128Merging
	OpAMD64VPMOVSQBMasked128_256Merging
	OpAMD64VPMOVSQBMasked128_512Merging
	OpAMD64VPMOVSQDMasked128_128Merging
	OpAMD64VPMOVSQDMasked128_256Merging
	OpAMD64VPMOVSQDMasked256Merging
	OpAMD64VPMOVSQWMasked128_128Merging
	OpAMD64VPMOVSQWMasked128_256Merging
	OpAMD64VPMOVSQWMasked128_512Merging
	OpAMD64VPMOVSWBMasked128_128Merging
	OpAMD64VPMOVSWBMasked128_256Merging
	OpAMD64VPMOVSWBMasked256Merging
	OpAMD64VPMOVSXBDMasked128Merging
	OpAMD64VPMOVSXBDMasked256Merging
	OpAMD64VPMOVSXBDMasked512Merging
	OpAMD64VPMOVSXBQMasked128Merging
	OpAMD64VPMOVSXBQMasked256Merging
	OpAMD64VPMOVSXBQMasked512Merging
	OpAMD64VPMOVSXBWMasked128Merging
	OpAMD64VPMOVSXBWMasked256Merging
	OpAMD64VPMOVSXBWMasked512Merging
	OpAMD64VPMOVSXDQMasked128Merging
	OpAMD64VPMOVSXDQMasked256Merging
	OpAMD64VPMOVSXDQMasked512Merging
	OpAMD64VPMOVSXWDMasked128Merging
	OpAMD64VPMOVSXWDMasked256Merging
	OpAMD64VPMOVSXWDMasked512Merging
	OpAMD64VPMOVSXWQMasked128Merging
	OpAMD64VPMOVSXWQMasked256Merging
	OpAMD64VPMOVSXWQMasked512Merging
	OpAMD64VPMOVUSDBMasked128_128Merging
	OpAMD64VPMOVUSDBMasked128_256Merging
	OpAMD64VPMOVUSDBMasked128_512Merging
	OpAMD64VPMOVUSDWMasked128_128Merging
	OpAMD64VPMOVUSDWMasked128_256Merging
	OpAMD64VPMOVUSDWMasked256Merging
	OpAMD64VPMOVUSQBMasked128_128Merging
	OpAMD64VPMOVUSQBMasked128_256Merging
	OpAMD64VPMOVUSQBMasked128_512Merging
	OpAMD64VPMOVUSQDMasked128_128Merging
	OpAMD64VPMOVUSQDMasked128_256Merging
	OpAMD64VPMOVUSQDMasked256Merging
	OpAMD64VPMOVUSQWMasked128_128Merging
	OpAMD64VPMOVUSQWMasked128_256Merging
	OpAMD64VPMOVUSQWMasked128_512Merging
	OpAMD64VPMOVUSWBMasked128_128Merging
	OpAMD64VPMOVUSWBMasked128_256Merging
	OpAMD64VPMOVUSWBMasked256Merging
	OpAMD64VPMOVWBMasked128_128Merging
	OpAMD64VPMOVWBMasked128_256Merging
	OpAMD64VPMOVWBMasked256Merging
	OpAMD64VPMOVZXBDMasked128Merging
	OpAMD64VPMOVZXBDMasked256Merging
	OpAMD64VPMOVZXBDMasked512Merging
	OpAMD64VPMOVZXBQMasked128Merging
	OpAMD64VPMOVZXBQMasked256Merging
	OpAMD64VPMOVZXBQMasked512Merging
	OpAMD64VPMOVZXBWMasked128Merging
	OpAMD64VPMOVZXBWMasked256Merging
	OpAMD64VPMOVZXBWMasked512Merging
	OpAMD64VPMOVZXDQMasked128Merging
	OpAMD64VPMOVZXDQMasked256Merging
	OpAMD64VPMOVZXDQMasked512Merging
	OpAMD64VPMOVZXWDMasked128Merging
	OpAMD64VPMOVZXWDMasked256Merging
	OpAMD64VPMOVZXWDMasked512Merging
	OpAMD64VPMOVZXWQMasked128Merging
	OpAMD64VPMOVZXWQMasked256Merging
	OpAMD64VPMOVZXWQMasked512Merging
	OpAMD64VPMULHUWMasked128Merging
	OpAMD64VPMULHUWMasked256Merging
	OpAMD64VPMULHUWMasked512Merging
	OpAMD64VPMULHWMasked128Merging
	OpAMD64VPMULHWMasked256Merging
	OpAMD64VPMULHWMasked512Merging
	OpAMD64VPMULLDMasked128Merging
	OpAMD64VPMULLDMasked256Merging
	OpAMD64VPMULLDMasked512Merging
	OpAMD64VPMULLQMasked128Merging
	OpAMD64VPMULLQMasked256Merging
	OpAMD64VPMULLQMasked512Merging
	OpAMD64VPMULLWMasked128Merging
	OpAMD64VPMULLWMasked256Merging
	OpAMD64VPMULLWMasked512Merging
	OpAMD64VPOPCNTBMasked128Merging
	OpAMD64VPOPCNTBMasked256Merging
	OpAMD64VPOPCNTBMasked512Merging
	OpAMD64VPOPCNTDMasked128Merging
	OpAMD64VPOPCNTDMasked256Merging
	OpAMD64VPOPCNTDMasked512Merging
	OpAMD64VPOPCNTQMasked128Merging
	OpAMD64VPOPCNTQMasked256Merging
	OpAMD64VPOPCNTQMasked512Merging
	OpAMD64VPOPCNTWMasked128Merging
	OpAMD64VPOPCNTWMasked256Merging
	OpAMD64VPOPCNTWMasked512Merging
	OpAMD64VPORDMasked128Merging
	OpAMD64VPORDMasked256Merging
	OpAMD64VPORDMasked512Merging
	OpAMD64VPORQMasked128Merging
	OpAMD64VPORQMasked256Merging
	OpAMD64VPORQMasked512Merging
	OpAMD64VPROLVDMasked128Merging
	OpAMD64VPROLVDMasked256Merging
	OpAMD64VPROLVDMasked512Merging
	OpAMD64VPROLVQMasked128Merging
	OpAMD64VPROLVQMasked256Merging
	OpAMD64VPROLVQMasked512Merging
	OpAMD64VPRORVDMasked128Merging
	OpAMD64VPRORVDMasked256Merging
	OpAMD64VPRORVDMasked512Merging
	OpAMD64VPRORVQMasked128Merging
	OpAMD64VPRORVQMasked256Merging
	OpAMD64VPRORVQMasked512Merging
	OpAMD64VPSHUFBMasked128Merging
	OpAMD64VPSHUFBMasked256Merging
	OpAMD64VPSHUFBMasked512Merging
	OpAMD64VPSLLVDMasked128Merging
	OpAMD64VPSLLVDMasked256Merging
	OpAMD64VPSLLVDMasked512Merging
	OpAMD64VPSLLVQMasked128Merging
	OpAMD64VPSLLVQMasked256Merging
	OpAMD64VPSLLVQMasked512Merging
	OpAMD64VPSLLVWMasked128Merging
	OpAMD64VPSLLVWMasked256Merging
	OpAMD64VPSLLVWMasked512Merging
	OpAMD64VPSRAVDMasked128Merging
	OpAMD64VPSRAVDMasked256Merging
	OpAMD64VPSRAVDMasked512Merging
	OpAMD64VPSRAVQMasked128Merging
	OpAMD64VPSRAVQMasked256Merging
	OpAMD64VPSRAVQMasked512Merging
	OpAMD64VPSRAVWMasked128Merging
	OpAMD64VPSRAVWMasked256Merging
	OpAMD64VPSRAVWMasked512Merging
	OpAMD64VPSRLVDMasked128Merging
	OpAMD64VPSRLVDMasked256Merging
	OpAMD64VPSRLVDMasked512Merging
	OpAMD64VPSRLVQMasked128Merging
	OpAMD64VPSRLVQMasked256Merging
	OpAMD64VPSRLVQMasked512Merging
	OpAMD64VPSRLVWMasked128Merging
	OpAMD64VPSRLVWMasked256Merging
	OpAMD64VPSRLVWMasked512Merging
	OpAMD64VPSUBBMasked128Merging
	OpAMD64VPSUBBMasked256Merging
	OpAMD64VPSUBBMasked512Merging
	OpAMD64VPSUBDMasked128Merging
	OpAMD64VPSUBDMasked256Merging
	OpAMD64VPSUBDMasked512Merging
	OpAMD64VPSUBQMasked128Merging
	OpAMD64VPSUBQMasked256Merging
	OpAMD64VPSUBQMasked512Merging
	OpAMD64VPSUBSBMasked128Merging
	OpAMD64VPSUBSBMasked256Merging
	OpAMD64VPSUBSBMasked512Merging
	OpAMD64VPSUBSWMasked128Merging
	OpAMD64VPSUBSWMasked256Merging
	OpAMD64VPSUBSWMasked512Merging
	OpAMD64VPSUBUSBMasked128Merging
	OpAMD64VPSUBUSBMasked256Merging
	OpAMD64VPSUBUSBMasked512Merging
	OpAMD64VPSUBUSWMasked128Merging
	OpAMD64VPSUBUSWMasked256Merging
	OpAMD64VPSUBUSWMasked512Merging
	OpAMD64VPSUBWMasked128Merging
	OpAMD64VPSUBWMasked256Merging
	OpAMD64VPSUBWMasked512Merging
	OpAMD64VPXORDMasked128Merging
	OpAMD64VPXORDMasked256Merging
	OpAMD64VPXORDMasked512Merging
	OpAMD64VPXORQMasked128Merging
	OpAMD64VPXORQMasked256Merging
	OpAMD64VPXORQMasked512Merging
	OpAMD64VRCP14PDMasked128Merging
	OpAMD64VRCP14PDMasked256Merging
	OpAMD64VRCP14PDMasked512Merging
	OpAMD64VRCP14PSMasked128Merging
	OpAMD64VRCP14PSMasked256Merging
	OpAMD64VRCP14PSMasked512Merging
	OpAMD64VRSQRT14PDMasked128Merging
	OpAMD64VRSQRT14PDMasked256Merging
	OpAMD64VRSQRT14PDMasked512Merging
	OpAMD64VRSQRT14PSMasked128Merging
	OpAMD64VRSQRT14PSMasked256Merging
	OpAMD64VRSQRT14PSMasked512Merging
	OpAMD64VSCALEFPDMasked128Merging
	OpAMD64VSCALEFPDMasked256Merging
	OpAMD64VSCALEFPDMasked512Merging
	OpAMD64VSCALEFPSMasked128Merging
	OpAMD64VSCALEFPSMasked256Merging
	OpAMD64VSCALEFPSMasked512Merging
	OpAMD64VSQRTPDMasked128Merging
	OpAMD64VSQRTPDMasked256Merging
	OpAMD64VSQRTPDMasked512Merging
	OpAMD64VSQRTPSMasked128Merging
	OpAMD64VSQRTPSMasked256Merging
	OpAMD64VSQRTPSMasked512Merging
	OpAMD64VSUBPDMasked128Merging
	OpAMD64VSUBPDMasked256Merging
	OpAMD64VSUBPDMasked512Merging
	OpAMD64VSUBPSMasked128Merging
	OpAMD64VSUBPSMasked256Merging
	OpAMD64VSUBPSMasked512Merging
	OpAMD64VPROLDMasked128Merging
	OpAMD64VPROLDMasked256Merging
	OpAMD64VPROLDMasked512Merging
	OpAMD64VPROLQMasked128Merging
	OpAMD64VPROLQMasked256Merging
	OpAMD64VPROLQMasked512Merging
	OpAMD64VPRORDMasked128Merging
	OpAMD64VPRORDMasked256Merging
	OpAMD64VPRORDMasked512Merging
	OpAMD64VPRORQMasked128Merging
	OpAMD64VPRORQMasked256Merging
	OpAMD64VPRORQMasked512Merging
	OpAMD64VPSHUFDMasked128Merging
	OpAMD64VPSHUFDMasked256Merging
	OpAMD64VPSHUFDMasked512Merging
	OpAMD64VPSHUFHWMasked128Merging
	OpAMD64VPSHUFHWMasked256Merging
	OpAMD64VPSHUFHWMasked512Merging
	OpAMD64VPSHUFLWMasked128Merging
	OpAMD64VPSHUFLWMasked256Merging
	OpAMD64VPSHUFLWMasked512Merging
	OpAMD64VPSLLDMasked128constMerging
	OpAMD64VPSLLDMasked256constMerging
	OpAMD64VPSLLDMasked512constMerging
	OpAMD64VPSLLQMasked128constMerging
	OpAMD64VPSLLQMasked256constMerging
	OpAMD64VPSLLQMasked512constMerging
	OpAMD64VPSLLWMasked128constMerging
	OpAMD64VPSLLWMasked256constMerging
	OpAMD64VPSLLWMasked512constMerging
	OpAMD64VPSRADMasked128constMerging
	OpAMD64VPSRADMasked256constMerging
	OpAMD64VPSRADMasked512constMerging
	OpAMD64VPSRAQMasked128constMerging
	OpAMD64VPSRAQMasked256constMerging
	OpAMD64VPSRAQMasked512constMerging
	OpAMD64VPSRAWMasked128constMerging
	OpAMD64VPSRAWMasked256constMerging
	OpAMD64VPSRAWMasked512constMerging
	OpAMD64VPSRLDMasked128constMerging
	OpAMD64VPSRLDMasked256constMerging
	OpAMD64VPSRLDMasked512constMerging
	OpAMD64VPSRLQMasked128constMerging
	OpAMD64VPSRLQMasked256constMerging
	OpAMD64VPSRLQMasked512constMerging
	OpAMD64VPSRLWMasked128constMerging
	OpAMD64VPSRLWMasked256constMerging
	OpAMD64VPSRLWMasked512constMerging
	OpAMD64VREDUCEPDMasked128Merging
	OpAMD64VREDUCEPDMasked256Merging
	OpAMD64VREDUCEPDMasked512Merging
	OpAMD64VREDUCEPSMasked128Merging
	OpAMD64VREDUCEPSMasked256Merging
	OpAMD64VREDUCEPSMasked512Merging
	OpAMD64VRNDSCALEPDMasked128Merging
	OpAMD64VRNDSCALEPDMasked256Merging
	OpAMD64VRNDSCALEPDMasked512Merging
	OpAMD64VRNDSCALEPSMasked128Merging
	OpAMD64VRNDSCALEPSMasked256Merging
	OpAMD64VRNDSCALEPSMasked512Merging

	OpARMADD
	OpARMADDconst
	OpARMSUB
	OpARMSUBconst
	OpARMRSB
	OpARMRSBconst
	OpARMMUL
	OpARMHMUL
	OpARMHMULU
	OpARMCALLudiv
	OpARMADDS
	OpARMADDSconst
	OpARMADC
	OpARMADCconst
	OpARMADCS
	OpARMSUBS
	OpARMSUBSconst
	OpARMRSBSconst
	OpARMSBC
	OpARMSBCconst
	OpARMRSCconst
	OpARMMULLU
	OpARMMULA
	OpARMMULS
	OpARMADDF
	OpARMADDD
	OpARMSUBF
	OpARMSUBD
	OpARMMULF
	OpARMMULD
	OpARMNMULF
	OpARMNMULD
	OpARMDIVF
	OpARMDIVD
	OpARMMULAF
	OpARMMULAD
	OpARMMULSF
	OpARMMULSD
	OpARMFMULAD
	OpARMAND
	OpARMANDconst
	OpARMOR
	OpARMORconst
	OpARMXOR
	OpARMXORconst
	OpARMBIC
	OpARMBICconst
	OpARMBFX
	OpARMBFXU
	OpARMMVN
	OpARMNEGF
	OpARMNEGD
	OpARMSQRTD
	OpARMSQRTF
	OpARMABSD
	OpARMCLZ
	OpARMREV
	OpARMREV16
	OpARMRBIT
	OpARMSLL
	OpARMSLLconst
	OpARMSRL
	OpARMSRLconst
	OpARMSRA
	OpARMSRAconst
	OpARMSRR
	OpARMSRRconst
	OpARMADDshiftLL
	OpARMADDshiftRL
	OpARMADDshiftRA
	OpARMSUBshiftLL
	OpARMSUBshiftRL
	OpARMSUBshiftRA
	OpARMRSBshiftLL
	OpARMRSBshiftRL
	OpARMRSBshiftRA
	OpARMANDshiftLL
	OpARMANDshiftRL
	OpARMANDshiftRA
	OpARMORshiftLL
	OpARMORshiftRL
	OpARMORshiftRA
	OpARMXORshiftLL
	OpARMXORshiftRL
	OpARMXORshiftRA
	OpARMXORshiftRR
	OpARMBICshiftLL
	OpARMBICshiftRL
	OpARMBICshiftRA
	OpARMMVNshiftLL
	OpARMMVNshiftRL
	OpARMMVNshiftRA
	OpARMADCshiftLL
	OpARMADCshiftRL
	OpARMADCshiftRA
	OpARMSBCshiftLL
	OpARMSBCshiftRL
	OpARMSBCshiftRA
	OpARMRSCshiftLL
	OpARMRSCshiftRL
	OpARMRSCshiftRA
	OpARMADDSshiftLL
	OpARMADDSshiftRL
	OpARMADDSshiftRA
	OpARMSUBSshiftLL
	OpARMSUBSshiftRL
	OpARMSUBSshiftRA
	OpARMRSBSshiftLL
	OpARMRSBSshiftRL
	OpARMRSBSshiftRA
	OpARMADDshiftLLreg
	OpARMADDshiftRLreg
	OpARMADDshiftRAreg
	OpARMSUBshiftLLreg
	OpARMSUBshiftRLreg
	OpARMSUBshiftRAreg
	OpARMRSBshiftLLreg
	OpARMRSBshiftRLreg
	OpARMRSBshiftRAreg
	OpARMANDshiftLLreg
	OpARMANDshiftRLreg
	OpARMANDshiftRAreg
	OpARMORshiftLLreg
	OpARMORshiftRLreg
	OpARMORshiftRAreg
	OpARMXORshiftLLreg
	OpARMXORshiftRLreg
	OpARMXORshiftRAreg
	OpARMBICshiftLLreg
	OpARMBICshiftRLreg
	OpARMBICshiftRAreg
	OpARMMVNshiftLLreg
	OpARMMVNshiftRLreg
	OpARMMVNshiftRAreg
	OpARMADCshiftLLreg
	OpARMADCshiftRLreg
	OpARMADCshiftRAreg
	OpARMSBCshiftLLreg
	OpARMSBCshiftRLreg
	OpARMSBCshiftRAreg
	OpARMRSCshiftLLreg
	OpARMRSCshiftRLreg
	OpARMRSCshiftRAreg
	OpARMADDSshiftLLreg
	OpARMADDSshiftRLreg
	OpARMADDSshiftRAreg
	OpARMSUBSshiftLLreg
	OpARMSUBSshiftRLreg
	OpARMSUBSshiftRAreg
	OpARMRSBSshiftLLreg
	OpARMRSBSshiftRLreg
	OpARMRSBSshiftRAreg
	OpARMCMP
	OpARMCMPconst
	OpARMCMN
	OpARMCMNconst
	OpARMTST
	OpARMTSTconst
	OpARMTEQ
	OpARMTEQconst
	OpARMCMPF
	OpARMCMPD
	OpARMCMPshiftLL
	OpARMCMPshiftRL
	OpARMCMPshiftRA
	OpARMCMNshiftLL
	OpARMCMNshiftRL
	OpARMCMNshiftRA
	OpARMTSTshiftLL
	OpARMTSTshiftRL
	OpARMTSTshiftRA
	OpARMTEQshiftLL
	OpARMTEQshiftRL
	OpARMTEQshiftRA
	OpARMCMPshiftLLreg
	OpARMCMPshiftRLreg
	OpARMCMPshiftRAreg
	OpARMCMNshiftLLreg
	OpARMCMNshiftRLreg
	OpARMCMNshiftRAreg
	OpARMTSTshiftLLreg
	OpARMTSTshiftRLreg
	OpARMTSTshiftRAreg
	OpARMTEQshiftLLreg
	OpARMTEQshiftRLreg
	OpARMTEQshiftRAreg
	OpARMCMPF0
	OpARMCMPD0
	OpARMMOVWconst
	OpARMMOVFconst
	OpARMMOVDconst
	OpARMMOVWaddr
	OpARMMOVBload
	OpARMMOVBUload
	OpARMMOVHload
	OpARMMOVHUload
	OpARMMOVWload
	OpARMMOVFload
	OpARMMOVDload
	OpARMMOVBstore
	OpARMMOVHstore
	OpARMMOVWstore
	OpARMMOVFstore
	OpARMMOVDstore
	OpARMMOVWloadidx
	OpARMMOVWloadshiftLL
	OpARMMOVWloadshiftRL
	OpARMMOVWloadshiftRA
	OpARMMOVBUloadidx
	OpARMMOVBloadidx
	OpARMMOVHUloadidx
	OpARMMOVHloadidx
	OpARMMOVWstoreidx
	OpARMMOVWstoreshiftLL
	OpARMMOVWstoreshiftRL
	OpARMMOVWstoreshiftRA
	OpARMMOVBstoreidx
	OpARMMOVHstoreidx
	OpARMMOVBreg
	OpARMMOVBUreg
	OpARMMOVHreg
	OpARMMOVHUreg
	OpARMMOVWreg
	OpARMMOVWnop
	OpARMMOVWF
	OpARMMOVWD
	OpARMMOVWUF
	OpARMMOVWUD
	OpARMMOVFW
	OpARMMOVDW
	OpARMMOVFWU
	OpARMMOVDWU
	OpARMMOVFD
	OpARMMOVDF
	OpARMCMOVWHSconst
	OpARMCMOVWLSconst
	OpARMSRAcond
	OpARMCALLstatic
	OpARMCALLtail
	OpARMCALLtailinter
	OpARMCALLclosure
	OpARMCALLinter
	OpARMLoweredNilCheck
	OpARMEqual
	OpARMNotEqual
	OpARMLessThan
	OpARMLessEqual
	OpARMGreaterThan
	OpARMGreaterEqual
	OpARMLessThanU
	OpARMLessEqualU
	OpARMGreaterThanU
	OpARMGreaterEqualU
	OpARMDUFFZERO
	OpARMDUFFCOPY
	OpARMLoweredZero
	OpARMLoweredMove
	OpARMLoweredGetClosurePtr
	OpARMLoweredGetCallerSP
	OpARMLoweredGetCallerPC
	OpARMLoweredPanicBoundsRR
	OpARMLoweredPanicBoundsRC
	OpARMLoweredPanicBoundsCR
	OpARMLoweredPanicBoundsCC
	OpARMLoweredPanicExtendRR
	OpARMLoweredPanicExtendRC
	OpARMFlagConstant
	OpARMInvertFlags
	OpARMLoweredWB

	OpARM64ADCSflags
	OpARM64ADCzerocarry
	OpARM64ADD
	OpARM64ADDconst
	OpARM64ADDSconstflags
	OpARM64ADDSflags
	OpARM64SUB
	OpARM64SUBconst
	OpARM64SBCSflags
	OpARM64SUBSflags
	OpARM64MUL
	OpARM64MULW
	OpARM64MNEG
	OpARM64MNEGW
	OpARM64MULH
	OpARM64UMULH
	OpARM64MULL
	OpARM64UMULL
	OpARM64DIV
	OpARM64UDIV
	OpARM64DIVW
	OpARM64UDIVW
	OpARM64MOD
	OpARM64UMOD
	OpARM64MODW
	OpARM64UMODW
	OpARM64FADDS
	OpARM64FADDD
	OpARM64FSUBS
	OpARM64FSUBD
	OpARM64FMULS
	OpARM64FMULD
	OpARM64FNMULS
	OpARM64FNMULD
	OpARM64FDIVS
	OpARM64FDIVD
	OpARM64AND
	OpARM64ANDconst
	OpARM64OR
	OpARM64ORconst
	OpARM64XOR
	OpARM64XORconst
	OpARM64BIC
	OpARM64EON
	OpARM64ORN
	OpARM64MVN
	OpARM64NEG
	OpARM64NEGSflags
	OpARM64NGCzerocarry
	OpARM64FABSD
	OpARM64FABSS
	OpARM64FNEGS
	OpARM64FNEGD
	OpARM64FSQRTD
	OpARM64FSQRTS
	OpARM64FMIND
	OpARM64FMINS
	OpARM64FMAXD
	OpARM64FMAXS
	OpARM64REV
	OpARM64REVW
	OpARM64REV16
	OpARM64REV16W
	OpARM64RBIT
	OpARM64RBITW
	OpARM64CLZ
	OpARM64CLZW
	OpARM64VCNT
	OpARM64VUADDLV
	OpARM64LoweredRound32F
	OpARM64LoweredRound64F
	OpARM64FMADDS
	OpARM64FMADDD
	OpARM64FNMADDS
	OpARM64FNMADDD
	OpARM64FMSUBS
	OpARM64FMSUBD
	OpARM64FNMSUBS
	OpARM64FNMSUBD
	OpARM64MADD
	OpARM64MADDW
	OpARM64MSUB
	OpARM64MSUBW
	OpARM64SLL
	OpARM64SLLconst
	OpARM64SRL
	OpARM64SRLconst
	OpARM64SRA
	OpARM64SRAconst
	OpARM64ROR
	OpARM64RORW
	OpARM64RORconst
	OpARM64RORWconst
	OpARM64EXTRconst
	OpARM64EXTRWconst
	OpARM64CMP
	OpARM64CMPconst
	OpARM64CMPW
	OpARM64CMPWconst
	OpARM64CMN
	OpARM64CMNconst
	OpARM64CMNW
	OpARM64CMNWconst
	OpARM64TST
	OpARM64TSTconst
	OpARM64TSTW
	OpARM64TSTWconst
	OpARM64FCMPS
	OpARM64FCMPD
	OpARM64FCMPS0
	OpARM64FCMPD0
	OpARM64MVNshiftLL
	OpARM64MVNshiftRL
	OpARM64MVNshiftRA
	OpARM64MVNshiftRO
	OpARM64NEGshiftLL
	OpARM64NEGshiftRL
	OpARM64NEGshiftRA
	OpARM64ADDshiftLL
	OpARM64ADDshiftRL
	OpARM64ADDshiftRA
	OpARM64SUBshiftLL
	OpARM64SUBshiftRL
	OpARM64SUBshiftRA
	OpARM64ANDshiftLL
	OpARM64ANDshiftRL
	OpARM64ANDshiftRA
	OpARM64ANDshiftRO
	OpARM64ORshiftLL
	OpARM64ORshiftRL
	OpARM64ORshiftRA
	OpARM64ORshiftRO
	OpARM64XORshiftLL
	OpARM64XORshiftRL
	OpARM64XORshiftRA
	OpARM64XORshiftRO
	OpARM64BICshiftLL
	OpARM64BICshiftRL
	OpARM64BICshiftRA
	OpARM64BICshiftRO
	OpARM64EONshiftLL
	OpARM64EONshiftRL
	OpARM64EONshiftRA
	OpARM64EONshiftRO
	OpARM64ORNshiftLL
	OpARM64ORNshiftRL
	OpARM64ORNshiftRA
	OpARM64ORNshiftRO
	OpARM64CMPshiftLL
	OpARM64CMPshiftRL
	OpARM64CMPshiftRA
	OpARM64CMNshiftLL
	OpARM64CMNshiftRL
	OpARM64CMNshiftRA
	OpARM64TSTshiftLL
	OpARM64TSTshiftRL
	OpARM64TSTshiftRA
	OpARM64TSTshiftRO
	OpARM64BFI
	OpARM64BFXIL
	OpARM64SBFIZ
	OpARM64SBFX
	OpARM64UBFIZ
	OpARM64UBFX
	OpARM64MOVDconst
	OpARM64FMOVSconst
	OpARM64FMOVDconst
	OpARM64MOVDaddr
	OpARM64MOVBload
	OpARM64MOVBUload
	OpARM64MOVHload
	OpARM64MOVHUload
	OpARM64MOVWload
	OpARM64MOVWUload
	OpARM64MOVDload
	OpARM64FMOVSload
	OpARM64FMOVDload
	OpARM64FMOVQload
	OpARM64LDP
	OpARM64LDPW
	OpARM64LDPSW
	OpARM64FLDPD
	OpARM64FLDPS
	OpARM64FLDPQ
	OpARM64MOVDloadidx
	OpARM64MOVWloadidx
	OpARM64MOVWUloadidx
	OpARM64MOVHloadidx
	OpARM64MOVHUloadidx
	OpARM64MOVBloadidx
	OpARM64MOVBUloadidx
	OpARM64FMOVSloadidx
	OpARM64FMOVDloadidx
	OpARM64MOVHloadidx2
	OpARM64MOVHUloadidx2
	OpARM64MOVWloadidx4
	OpARM64MOVWUloadidx4
	OpARM64MOVDloadidx8
	OpARM64FMOVSloadidx4
	OpARM64FMOVDloadidx8
	OpARM64MOVBstore
	OpARM64MOVHstore
	OpARM64MOVWstore
	OpARM64MOVDstore
	OpARM64FMOVSstore
	OpARM64FMOVDstore
	OpARM64FMOVQstore
	OpARM64STP
	OpARM64STPW
	OpARM64FSTPD
	OpARM64FSTPS
	OpARM64FSTPQ
	OpARM64MOVBstoreidx
	OpARM64MOVHstoreidx
	OpARM64MOVWstoreidx
	OpARM64MOVDstoreidx
	OpARM64FMOVSstoreidx
	OpARM64FMOVDstoreidx
	OpARM64MOVHstoreidx2
	OpARM64MOVWstoreidx4
	OpARM64MOVDstoreidx8
	OpARM64FMOVSstoreidx4
	OpARM64FMOVDstoreidx8
	OpARM64FMOVDgpfp
	OpARM64FMOVDfpgp
	OpARM64FMOVSgpfp
	OpARM64FMOVSfpgp
	OpARM64MOVBreg
	OpARM64MOVBUreg
	OpARM64MOVHreg
	OpARM64MOVHUreg
	OpARM64MOVWreg
	OpARM64MOVWUreg
	OpARM64MOVDreg
	OpARM64MOVDnop
	OpARM64SCVTFWS
	OpARM64SCVTFWD
	OpARM64UCVTFWS
	OpARM64UCVTFWD
	OpARM64SCVTFS
	OpARM64SCVTFD
	OpARM64UCVTFS
	OpARM64UCVTFD
	OpARM64FCVTZSSW
	OpARM64FCVTZSDW
	OpARM64FCVTZUSW
	OpARM64FCVTZUDW
	OpARM64FCVTZSS
	OpARM64FCVTZSD
	OpARM64FCVTZUS
	OpARM64FCVTZUD
	OpARM64FCVTSD
	OpARM64FCVTDS
	OpARM64FRINTAD
	OpARM64FRINTMD
	OpARM64FRINTND
	OpARM64FRINTPD
	OpARM64FRINTZD
	OpARM64FRINTAS
	OpARM64FRINTMS
	OpARM64FRINTNS
	OpARM64FRINTPS
	OpARM64FRINTZS
	OpARM64CSEL
	OpARM64CSEL0
	OpARM64CSINC
	OpARM64CSINV
	OpARM64CSNEG
	OpARM64CSETM
	OpARM64CCMP
	OpARM64CCMN
	OpARM64CCMPconst
	OpARM64CCMNconst
	OpARM64CCMPW
	OpARM64CCMNW
	OpARM64CCMPWconst
	OpARM64CCMNWconst
	OpARM64CALLstatic
	OpARM64CALLtail
	OpARM64CALLtailinter
	OpARM64CALLclosure
	OpARM64CALLinter
	OpARM64LoweredNilCheck
	OpARM64LoweredMemEq
	OpARM64Equal
	OpARM64NotEqual
	OpARM64LessThan
	OpARM64LessEqual
	OpARM64GreaterThan
	OpARM64GreaterEqual
	OpARM64LessThanU
	OpARM64LessEqualU
	OpARM64GreaterThanU
	OpARM64GreaterEqualU
	OpARM64LessThanF
	OpARM64LessEqualF
	OpARM64GreaterThanF
	OpARM64GreaterEqualF
	OpARM64NotLessThanF
	OpARM64NotLessEqualF
	OpARM64NotGreaterThanF
	OpARM64NotGreaterEqualF
	OpARM64LessThanNoov
	OpARM64GreaterEqualNoov
	OpARM64LoweredZero
	OpARM64LoweredZeroLoop
	OpARM64LoweredMove
	OpARM64LoweredMoveLoop
	OpARM64LoweredGetClosurePtr
	OpARM64LoweredGetCallerSP
	OpARM64LoweredGetCallerPC
	OpARM64FlagConstant
	OpARM64InvertFlags
	OpARM64LDAR
	OpARM64LDARB
	OpARM64LDARW
	OpARM64STLRB
	OpARM64STLR
	OpARM64STLRW
	OpARM64LoweredAtomicExchange64
	OpARM64LoweredAtomicExchange32
	OpARM64LoweredAtomicExchange8
	OpARM64LoweredAtomicExchange64Variant
	OpARM64LoweredAtomicExchange32Variant
	OpARM64LoweredAtomicExchange8Variant
	OpARM64LoweredAtomicAdd64
	OpARM64LoweredAtomicAdd32
	OpARM64LoweredAtomicAdd64Variant
	OpARM64LoweredAtomicAdd32Variant
	OpARM64LoweredAtomicCas64
	OpARM64LoweredAtomicCas32
	OpARM64LoweredAtomicCas64Variant
	OpARM64LoweredAtomicCas32Variant
	OpARM64LoweredAtomicAnd8
	OpARM64LoweredAtomicOr8
	OpARM64LoweredAtomicAnd64
	OpARM64LoweredAtomicOr64
	OpARM64LoweredAtomicAnd32
	OpARM64LoweredAtomicOr32
	OpARM64LoweredAtomicAnd8Variant
	OpARM64LoweredAtomicOr8Variant
	OpARM64LoweredAtomicAnd64Variant
	OpARM64LoweredAtomicOr64Variant
	OpARM64LoweredAtomicAnd32Variant
	OpARM64LoweredAtomicOr32Variant
	OpARM64LoweredWB
	OpARM64LoweredPanicBoundsRR
	OpARM64LoweredPanicBoundsRC
	OpARM64LoweredPanicBoundsCR
	OpARM64LoweredPanicBoundsCC
	OpARM64PRFM
	OpARM64DMB
	OpARM64ZERO
	OpARM64VMOVI16B
	OpARM64VABS2D
	OpARM64VABS4S
	OpARM64VABS8H
	OpARM64VABS16B
	OpARM64VADD2D
	OpARM64VADD4S
	OpARM64VADD8H
	OpARM64VADD16B
	OpARM64VADDP2D
	OpARM64VADDP4S
	OpARM64VADDP8H
	OpARM64VADDV4S
	OpARM64VADDV8H
	OpARM64VADDV16B
	OpARM64VAND16B
	OpARM64VBIC16B
	OpARM64VBIF16B
	OpARM64VBIT16B
	OpARM64VCLS4S
	OpARM64VCLS8H
	OpARM64VCLS16B
	OpARM64VCLZ4S
	OpARM64VCLZ8H
	OpARM64VCLZ16B
	OpARM64VCMEQ2D
	OpARM64VCMEQ4S
	OpARM64VCMEQ8H
	OpARM64VCMEQ16B
	OpARM64VCMGE2D
	OpARM64VCMGE4S
	OpARM64VCMGE8H
	OpARM64VCMGE16B
	OpARM64VCMGT2D
	OpARM64VCMGT4S
	OpARM64VCMGT8H
	OpARM64VCMGT16B
	OpARM64VCMHI2D
	OpARM64VCMHI4S
	OpARM64VCMHI8H
	OpARM64VCMHI16B
	OpARM64VCMHS2D
	OpARM64VCMHS4S
	OpARM64VCMHS8H
	OpARM64VCMHS16B
	OpARM64VCNT16B
	OpARM64VEOR16B
	OpARM64VFABS2D
	OpARM64VFABS4S
	OpARM64VFADD2D
	OpARM64VFADD4S
	OpARM64VFADDP2D
	OpARM64VFADDP4S
	OpARM64VFCMEQ2D
	OpARM64VFCMEQ4S
	OpARM64VFCMGE2D
	OpARM64VFCMGE4S
	OpARM64VFCMGT2D
	OpARM64VFCMGT4S
	OpARM64VFCVTL2_4S
	OpARM64VFCVTL4S
	OpARM64VFCVTN2D
	OpARM64VFCVTN2_2D
	OpARM64VFCVTZS2D
	OpARM64VFCVTZS4S
	OpARM64VFCVTZU2D
	OpARM64VFCVTZU4S
	OpARM64VFDIV2D
	OpARM64VFDIV4S
	OpARM64VFMAX2D
	OpARM64VFMAX4S
	OpARM64VFMAXV4S
	OpARM64VFMIN2D
	OpARM64VFMIN4S
	OpARM64VFMINV4S
	OpARM64VFMLA2D
	OpARM64VFMLA4S
	OpARM64VFMUL2D
	OpARM64VFMUL4S
	OpARM64VFNEG2D
	OpARM64VFNEG4S
	OpARM64VFRINTM2D
	OpARM64VFRINTM4S
	OpARM64VFRINTN2D
	OpARM64VFRINTN4S
	OpARM64VFRINTP2D
	OpARM64VFRINTP4S
	OpARM64VFRINTZ2D
	OpARM64VFRINTZ4S
	OpARM64VFSQRT2D
	OpARM64VFSQRT4S
	OpARM64VFSUB2D
	OpARM64VFSUB4S
	OpARM64VMLA4S
	OpARM64VMLA8H
	OpARM64VMLA16B
	OpARM64VMUL4S
	OpARM64VMUL8H
	OpARM64VMUL16B
	OpARM64VNEG2D
	OpARM64VNEG4S
	OpARM64VNEG8H
	OpARM64VNEG16B
	OpARM64VNOT16B
	OpARM64VORN16B
	OpARM64VORR16B
	OpARM64VPMULL2D
	OpARM64VPMULL2_2D
	OpARM64VSCVTF2D
	OpARM64VSCVTF4S
	OpARM64VSMAX4S
	OpARM64VSMAX8H
	OpARM64VSMAX16B
	OpARM64VSMAXV4S
	OpARM64VSMAXV8H
	OpARM64VSMAXV16B
	OpARM64VSMIN4S
	OpARM64VSMIN8H
	OpARM64VSMIN16B
	OpARM64VSMINV4S
	OpARM64VSMINV8H
	OpARM64VSMINV16B
	OpARM64VSMULL2_4S
	OpARM64VSMULL2_8H
	OpARM64VSMULL2_16B
	OpARM64VSMULL4S
	OpARM64VSMULL8H
	OpARM64VSMULL16B
	OpARM64VSQADD2D
	OpARM64VSQADD4S
	OpARM64VSQADD8H
	OpARM64VSQADD16B
	OpARM64VSQSHL2D
	OpARM64VSQSHL4S
	OpARM64VSQSHL8H
	OpARM64VSQSHL16B
	OpARM64VSQSUB2D
	OpARM64VSQSUB4S
	OpARM64VSQSUB8H
	OpARM64VSQSUB16B
	OpARM64VSQXTN2D
	OpARM64VSQXTN2_2D
	OpARM64VSQXTN2_4S
	OpARM64VSQXTN2_8H
	OpARM64VSQXTN4S
	OpARM64VSQXTN8H
	OpARM64VSQXTUN2D
	OpARM64VSQXTUN2_2D
	OpARM64VSQXTUN2_4S
	OpARM64VSQXTUN2_8H
	OpARM64VSQXTUN4S
	OpARM64VSQXTUN8H
	OpARM64VSRHADD4S
	OpARM64VSRHADD8H
	OpARM64VSRHADD16B
	OpARM64VSSHL2D
	OpARM64VSSHL4S
	OpARM64VSSHL8H
	OpARM64VSSHL16B
	OpARM64VSUB2D
	OpARM64VSUB4S
	OpARM64VSUB8H
	OpARM64VSUB16B
	OpARM64VSXTL2_4S
	OpARM64VSXTL2_8H
	OpARM64VSXTL2_16B
	OpARM64VSXTL4S
	OpARM64VSXTL8H
	OpARM64VSXTL16B
	OpARM64VTBL16B
	OpARM64VTBX16B
	OpARM64VTRN12D
	OpARM64VTRN14S
	OpARM64VTRN18H
	OpARM64VTRN22D
	OpARM64VTRN24S
	OpARM64VTRN28H
	OpARM64VTRN116B
	OpARM64VTRN216B
	OpARM64VUCVTF2D
	OpARM64VUCVTF4S
	OpARM64VUMAX4S
	OpARM64VUMAX8H
	OpARM64VUMAX16B
	OpARM64VUMAXV4S
	OpARM64VUMAXV8H
	OpARM64VUMAXV16B
	OpARM64VUMIN4S
	OpARM64VUMIN8H
	OpARM64VUMIN16B
	OpARM64VUMINV4S
	OpARM64VUMINV8H
	OpARM64VUMINV16B
	OpARM64VUMULL2_4S
	OpARM64VUMULL2_8H
	OpARM64VUMULL2_16B
	OpARM64VUMULL4S
	OpARM64VUMULL8H
	OpARM64VUMULL16B
	OpARM64VUQADD2D
	OpARM64VUQADD4S
	OpARM64VUQADD8H
	OpARM64VUQADD16B
	OpARM64VUQSHL2D
	OpARM64VUQSHL4S
	OpARM64VUQSHL8H
	OpARM64VUQSHL16B
	OpARM64VUQSUB2D
	OpARM64VUQSUB4S
	OpARM64VUQSUB8H
	OpARM64VUQSUB16B
	OpARM64VUQXTN2D
	OpARM64VUQXTN2_2D
	OpARM64VUQXTN2_4S
	OpARM64VUQXTN2_8H
	OpARM64VUQXTN4S
	OpARM64VUQXTN8H
	OpARM64VURHADD4S
	OpARM64VURHADD8H
	OpARM64VURHADD16B
	OpARM64VUSHL2D
	OpARM64VUSHL4S
	OpARM64VUSHL8H
	OpARM64VUSHL16B
	OpARM64VUXTL2_4S
	OpARM64VUXTL2_8H
	OpARM64VUXTL2_16B
	OpARM64VUXTL4S
	OpARM64VUXTL8H
	OpARM64VUXTL16B
	OpARM64VUZP12D
	OpARM64VUZP14S
	OpARM64VUZP18H
	OpARM64VUZP22D
	OpARM64VUZP24S
	OpARM64VUZP28H
	OpARM64VUZP116B
	OpARM64VUZP216B
	OpARM64VXTN2D
	OpARM64VXTN2_2D
	OpARM64VXTN2_4S
	OpARM64VXTN2_8H
	OpARM64VXTN4S
	OpARM64VXTN8H
	OpARM64VZIP12D
	OpARM64VZIP14S
	OpARM64VZIP18H
	OpARM64VZIP22D
	OpARM64VZIP24S
	OpARM64VZIP28H
	OpARM64VZIP116B
	OpARM64VZIP216B
	OpARM64VDUPBbcast
	OpARM64VDUPDbcast
	OpARM64VDUPDextr
	OpARM64VDUPHbcast
	OpARM64VDUPSbcast
	OpARM64VDUPSextr
	OpARM64VEXT16B
	OpARM64VMOVBextr
	OpARM64VMOVBins
	OpARM64VMOVDextr
	OpARM64VMOVDins
	OpARM64VMOVDins0
	OpARM64VMOVHextr
	OpARM64VMOVHins
	OpARM64VMOVSextr
	OpARM64VMOVSins
	OpARM64VMOVSins0
	OpARM64VSHL2D
	OpARM64VSHL4S
	OpARM64VSHL8H
	OpARM64VSHL16B
	OpARM64VSHRN2D
	OpARM64VSHRN2_2D
	OpARM64VSHRN2_4S
	OpARM64VSHRN2_8H
	OpARM64VSHRN4S
	OpARM64VSHRN8H
	OpARM64VSQSHL2Dconst
	OpARM64VSQSHL4Sconst
	OpARM64VSQSHL8Hconst
	OpARM64VSQSHL16Bconst
	OpARM64VSSHLL2_4S
	OpARM64VSSHLL2_8H
	OpARM64VSSHLL2_16B
	OpARM64VSSHLL4S
	OpARM64VSSHLL8H
	OpARM64VSSHLL16B
	OpARM64VSSHR2D
	OpARM64VSSHR4S
	OpARM64VSSHR8H
	OpARM64VSSHR16B
	OpARM64VUQSHL2Dconst
	OpARM64VUQSHL4Sconst
	OpARM64VUQSHL8Hconst
	OpARM64VUQSHL16Bconst
	OpARM64VUSHLL2_4S
	OpARM64VUSHLL2_8H
	OpARM64VUSHLL2_16B
	OpARM64VUSHLL4S
	OpARM64VUSHLL8H
	OpARM64VUSHLL16B
	OpARM64VUSHR2D
	OpARM64VUSHR4S
	OpARM64VUSHR8H
	OpARM64VUSHR16B

	OpLOONG64NEGV
	OpLOONG64NEGF
	OpLOONG64NEGD
	OpLOONG64SQRTD
	OpLOONG64SQRTF
	OpLOONG64ABSF
	OpLOONG64ABSD
	OpLOONG64CLZW
	OpLOONG64CLZV
	OpLOONG64CTZW
	OpLOONG64CTZV
	OpLOONG64REVB2H
	OpLOONG64REVB2W
	OpLOONG64REVB4H
	OpLOONG64REVBV
	OpLOONG64BITREV4B
	OpLOONG64BITREVW
	OpLOONG64BITREVV
	OpLOONG64VPCNT64
	OpLOONG64VPCNT32
	OpLOONG64VPCNT16
	OpLOONG64ADDV
	OpLOONG64ADDVconst
	OpLOONG64ADDV16const
	OpLOONG64SUBV
	OpLOONG64SUBVconst
	OpLOONG64MULV
	OpLOONG64MULHV
	OpLOONG64MULHVU
	OpLOONG64MULH
	OpLOONG64MULHU
	OpLOONG64DIVV
	OpLOONG64DIVVU
	OpLOONG64REMV
	OpLOONG64REMVU
	OpLOONG64MULWVW
	OpLOONG64MULWVWU
	OpLOONG64ADDF
	OpLOONG64ADDD
	OpLOONG64SUBF
	OpLOONG64SUBD
	OpLOONG64MULF
	OpLOONG64MULD
	OpLOONG64DIVF
	OpLOONG64DIVD
	OpLOONG64AND
	OpLOONG64ANDconst
	OpLOONG64OR
	OpLOONG64ORconst
	OpLOONG64XOR
	OpLOONG64XORconst
	OpLOONG64NOR
	OpLOONG64NORconst
	OpLOONG64ANDN
	OpLOONG64ORN
	OpLOONG64FMADDF
	OpLOONG64FMADDD
	OpLOONG64FMSUBF
	OpLOONG64FMSUBD
	OpLOONG64FNMADDF
	OpLOONG64FNMADDD
	OpLOONG64FNMSUBF
	OpLOONG64FNMSUBD
	OpLOONG64FMINF
	OpLOONG64FMIND
	OpLOONG64FMAXF
	OpLOONG64FMAXD
	OpLOONG64MASKEQZ
	OpLOONG64MASKNEZ
	OpLOONG64FCOPYSGD
	OpLOONG64SLL
	OpLOONG64SLLV
	OpLOONG64SLLconst
	OpLOONG64SLLVconst
	OpLOONG64SRL
	OpLOONG64SRLV
	OpLOONG64SRLconst
	OpLOONG64SRLVconst
	OpLOONG64SRA
	OpLOONG64SRAV
	OpLOONG64SRAconst
	OpLOONG64SRAVconst
	OpLOONG64ROTR
	OpLOONG64ROTRV
	OpLOONG64ROTRconst
	OpLOONG64ROTRVconst
	OpLOONG64SGT
	OpLOONG64SGTconst
	OpLOONG64SGTU
	OpLOONG64SGTUconst
	OpLOONG64CMPEQF
	OpLOONG64CMPEQD
	OpLOONG64CMPGEF
	OpLOONG64CMPGED
	OpLOONG64CMPGTF
	OpLOONG64CMPGTD
	OpLOONG64BSTRPICKW
	OpLOONG64BSTRPICKV
	OpLOONG64MOVVconst
	OpLOONG64MOVFconst
	OpLOONG64MOVDconst
	OpLOONG64MOVVaddr
	OpLOONG64MOVBload
	OpLOONG64MOVBUload
	OpLOONG64MOVHload
	OpLOONG64MOVHUload
	OpLOONG64MOVWload
	OpLOONG64MOVWUload
	OpLOONG64MOVVload
	OpLOONG64MOVFload
	OpLOONG64MOVDload
	OpLOONG64MOVVloadidx
	OpLOONG64MOVWloadidx
	OpLOONG64MOVWUloadidx
	OpLOONG64MOVHloadidx
	OpLOONG64MOVHUloadidx
	OpLOONG64MOVBloadidx
	OpLOONG64MOVBUloadidx
	OpLOONG64MOVFloadidx
	OpLOONG64MOVDloadidx
	OpLOONG64MOVBstore
	OpLOONG64MOVHstore
	OpLOONG64MOVWstore
	OpLOONG64MOVVstore
	OpLOONG64MOVFstore
	OpLOONG64MOVDstore
	OpLOONG64MOVBstoreidx
	OpLOONG64MOVHstoreidx
	OpLOONG64MOVWstoreidx
	OpLOONG64MOVVstoreidx
	OpLOONG64MOVFstoreidx
	OpLOONG64MOVDstoreidx
	OpLOONG64MOVWfpgp
	OpLOONG64MOVWgpfp
	OpLOONG64MOVVfpgp
	OpLOONG64MOVVgpfp
	OpLOONG64MOVBreg
	OpLOONG64MOVBUreg
	OpLOONG64MOVHreg
	OpLOONG64MOVHUreg
	OpLOONG64MOVWreg
	OpLOONG64MOVWUreg
	OpLOONG64MOVVreg
	OpLOONG64MOVVnop
	OpLOONG64MOVWF
	OpLOONG64MOVWD
	OpLOONG64MOVVF
	OpLOONG64MOVVD
	OpLOONG64TRUNCFW
	OpLOONG64TRUNCDW
	OpLOONG64TRUNCFV
	OpLOONG64TRUNCDV
	OpLOONG64MOVFD
	OpLOONG64MOVDF
	OpLOONG64FRINTND
	OpLOONG64FRINTMD
	OpLOONG64FRINTPD
	OpLOONG64FRINTZD
	OpLOONG64LoweredRound32F
	OpLOONG64LoweredRound64F
	OpLOONG64CALLstatic
	OpLOONG64CALLtail
	OpLOONG64CALLtailinter
	OpLOONG64CALLclosure
	OpLOONG64CALLinter
	OpLOONG64LoweredZero
	OpLOONG64LoweredZeroLoop
	OpLOONG64LoweredMove
	OpLOONG64LoweredMoveLoop
	OpLOONG64LoweredAtomicLoad8
	OpLOONG64LoweredAtomicLoad32
	OpLOONG64LoweredAtomicLoad64
	OpLOONG64LoweredAtomicStore8
	OpLOONG64LoweredAtomicStore32
	OpLOONG64LoweredAtomicStore64
	OpLOONG64LoweredAtomicStore8Variant
	OpLOONG64LoweredAtomicStore32Variant
	OpLOONG64LoweredAtomicStore64Variant
	OpLOONG64LoweredAtomicExchange32
	OpLOONG64LoweredAtomicExchange64
	OpLOONG64LoweredAtomicExchange8Variant
	OpLOONG64LoweredAtomicAdd32
	OpLOONG64LoweredAtomicAdd64
	OpLOONG64LoweredAtomicCas32
	OpLOONG64LoweredAtomicCas64
	OpLOONG64LoweredAtomicCas64Variant
	OpLOONG64LoweredAtomicCas32Variant
	OpLOONG64LoweredAtomicAnd32
	OpLOONG64LoweredAtomicOr32
	OpLOONG64LoweredAtomicAnd32value
	OpLOONG64LoweredAtomicAnd64value
	OpLOONG64LoweredAtomicOr32value
	OpLOONG64LoweredAtomicOr64value
	OpLOONG64LoweredNilCheck
	OpLOONG64FPFlagTrue
	OpLOONG64FPFlagFalse
	OpLOONG64LoweredGetClosurePtr
	OpLOONG64LoweredGetCallerSP
	OpLOONG64LoweredGetCallerPC
	OpLOONG64LoweredWB
	OpLOONG64LoweredPubBarrier
	OpLOONG64LoweredPanicBoundsRR
	OpLOONG64LoweredPanicBoundsRC
	OpLOONG64LoweredPanicBoundsCR
	OpLOONG64LoweredPanicBoundsCC
	OpLOONG64PRELD
	OpLOONG64PRELDX
	OpLOONG64ADDshiftLLV
	OpLOONG64ZERO

	OpMIPSADD
	OpMIPSADDconst
	OpMIPSSUB
	OpMIPSSUBconst
	OpMIPSMUL
	OpMIPSMULT
	OpMIPSMULTU
	OpMIPSDIV
	OpMIPSDIVU
	OpMIPSADDF
	OpMIPSADDD
	OpMIPSSUBF
	OpMIPSSUBD
	OpMIPSMULF
	OpMIPSMULD
	OpMIPSDIVF
	OpMIPSDIVD
	OpMIPSAND
	OpMIPSANDconst
	OpMIPSOR
	OpMIPSORconst
	OpMIPSXOR
	OpMIPSXORconst
	OpMIPSNOR
	OpMIPSNEG
	OpMIPSNEGF
	OpMIPSNEGD
	OpMIPSABSD
	OpMIPSSQRTD
	OpMIPSSQRTF
	OpMIPSSLL
	OpMIPSSLLconst
	OpMIPSSRL
	OpMIPSSRLconst
	OpMIPSSRA
	OpMIPSSRAconst
	OpMIPSCLZ
	OpMIPSSGT
	OpMIPSSGTconst
	OpMIPSSGTzero
	OpMIPSSGTU
	OpMIPSSGTUconst
	OpMIPSSGTUzero
	OpMIPSCMPEQF
	OpMIPSCMPEQD
	OpMIPSCMPGEF
	OpMIPSCMPGED
	OpMIPSCMPGTF
	OpMIPSCMPGTD
	OpMIPSMOVWconst
	OpMIPSMOVFconst
	OpMIPSMOVDconst
	OpMIPSMOVWaddr
	OpMIPSMOVBload
	OpMIPSMOVBUload
	OpMIPSMOVHload
	OpMIPSMOVHUload
	OpMIPSMOVWload
	OpMIPSMOVFload
	OpMIPSMOVDload
	OpMIPSMOVBstore
	OpMIPSMOVHstore
	OpMIPSMOVWstore
	OpMIPSMOVFstore
	OpMIPSMOVDstore
	OpMIPSMOVBstorezero
	OpMIPSMOVHstorezero
	OpMIPSMOVWstorezero
	OpMIPSMOVWfpgp
	OpMIPSMOVWgpfp
	OpMIPSMOVBreg
	OpMIPSMOVBUreg
	OpMIPSMOVHreg
	OpMIPSMOVHUreg
	OpMIPSMOVWreg
	OpMIPSMOVWnop
	OpMIPSCMOVZ
	OpMIPSCMOVZzero
	OpMIPSMOVWF
	OpMIPSMOVWD
	OpMIPSTRUNCFW
	OpMIPSTRUNCDW
	OpMIPSMOVFD
	OpMIPSMOVDF
	OpMIPSCALLstatic
	OpMIPSCALLtail
	OpMIPSCALLtailinter
	OpMIPSCALLclosure
	OpMIPSCALLinter
	OpMIPSLoweredAtomicLoad8
	OpMIPSLoweredAtomicLoad32
	OpMIPSLoweredAtomicStore8
	OpMIPSLoweredAtomicStore32
	OpMIPSLoweredAtomicStorezero
	OpMIPSLoweredAtomicExchange
	OpMIPSLoweredAtomicAdd
	OpMIPSLoweredAtomicAddconst
	OpMIPSLoweredAtomicCas
	OpMIPSLoweredAtomicAnd
	OpMIPSLoweredAtomicOr
	OpMIPSLoweredZero
	OpMIPSLoweredMove
	OpMIPSLoweredNilCheck
	OpMIPSFPFlagTrue
	OpMIPSFPFlagFalse
	OpMIPSLoweredGetClosurePtr
	OpMIPSLoweredGetCallerSP
	OpMIPSLoweredGetCallerPC
	OpMIPSLoweredWB
	OpMIPSLoweredPubBarrier
	OpMIPSLoweredPanicBoundsRR
	OpMIPSLoweredPanicBoundsRC
	OpMIPSLoweredPanicBoundsCR
	OpMIPSLoweredPanicBoundsCC
	OpMIPSLoweredPanicExtendRR
	OpMIPSLoweredPanicExtendRC

	OpMIPS64ADDV
	OpMIPS64ADDVconst
	OpMIPS64SUBV
	OpMIPS64SUBVconst
	OpMIPS64MULV
	OpMIPS64MULVU
	OpMIPS64DIVV
	OpMIPS64DIVVU
	OpMIPS64ADDF
	OpMIPS64ADDD
	OpMIPS64SUBF
	OpMIPS64SUBD
	OpMIPS64MULF
	OpMIPS64MULD
	OpMIPS64DIVF
	OpMIPS64DIVD
	OpMIPS64AND
	OpMIPS64ANDconst
	OpMIPS64OR
	OpMIPS64ORconst
	OpMIPS64XOR
	OpMIPS64XORconst
	OpMIPS64NOR
	OpMIPS64NEGV
	OpMIPS64NEGF
	OpMIPS64NEGD
	OpMIPS64ABSF
	OpMIPS64ABSD
	OpMIPS64SQRTD
	OpMIPS64SQRTF
	OpMIPS64SLLV
	OpMIPS64SLLVconst
	OpMIPS64SRLV
	OpMIPS64SRLVconst
	OpMIPS64SRAV
	OpMIPS64SRAVconst
	OpMIPS64SGT
	OpMIPS64SGTconst
	OpMIPS64SGTU
	OpMIPS64SGTUconst
	OpMIPS64CMPEQF
	OpMIPS64CMPEQD
	OpMIPS64CMPGEF
	OpMIPS64CMPGED
	OpMIPS64CMPGTF
	OpMIPS64CMPGTD
	OpMIPS64MOVVconst
	OpMIPS64MOVFconst
	OpMIPS64MOVDconst
	OpMIPS64MOVVaddr
	OpMIPS64MOVBload
	OpMIPS64MOVBUload
	OpMIPS64MOVHload
	OpMIPS64MOVHUload
	OpMIPS64MOVWload
	OpMIPS64MOVWUload
	OpMIPS64MOVVload
	OpMIPS64MOVFload
	OpMIPS64MOVDload
	OpMIPS64MOVBstore
	OpMIPS64MOVHstore
	OpMIPS64MOVWstore
	OpMIPS64MOVVstore
	OpMIPS64MOVFstore
	OpMIPS64MOVDstore
	OpMIPS64ZERO
	OpMIPS64MOVWfpgp
	OpMIPS64MOVWgpfp
	OpMIPS64MOVVfpgp
	OpMIPS64MOVVgpfp
	OpMIPS64MOVBreg
	OpMIPS64MOVBUreg
	OpMIPS64MOVHreg
	OpMIPS64MOVHUreg
	OpMIPS64MOVWreg
	OpMIPS64MOVWUreg
	OpMIPS64MOVVreg
	OpMIPS64MOVVnop
	OpMIPS64MOVWF
	OpMIPS64MOVWD
	OpMIPS64MOVVF
	OpMIPS64MOVVD
	OpMIPS64TRUNCFW
	OpMIPS64TRUNCDW
	OpMIPS64TRUNCFV
	OpMIPS64TRUNCDV
	OpMIPS64MOVFD
	OpMIPS64MOVDF
	OpMIPS64CALLstatic
	OpMIPS64CALLtail
	OpMIPS64CALLtailinter
	OpMIPS64CALLclosure
	OpMIPS64CALLinter
	OpMIPS64DUFFZERO
	OpMIPS64DUFFCOPY
	OpMIPS64LoweredZero
	OpMIPS64LoweredMove
	OpMIPS64LoweredAtomicAnd32
	OpMIPS64LoweredAtomicOr32
	OpMIPS64LoweredAtomicLoad8
	OpMIPS64LoweredAtomicLoad32
	OpMIPS64LoweredAtomicLoad64
	OpMIPS64LoweredAtomicStore8
	OpMIPS64LoweredAtomicStore32
	OpMIPS64LoweredAtomicStore64
	OpMIPS64LoweredAtomicStorezero32
	OpMIPS64LoweredAtomicStorezero64
	OpMIPS64LoweredAtomicExchange32
	OpMIPS64LoweredAtomicExchange64
	OpMIPS64LoweredAtomicAdd32
	OpMIPS64LoweredAtomicAdd64
	OpMIPS64LoweredAtomicAddconst32
	OpMIPS64LoweredAtomicAddconst64
	OpMIPS64LoweredAtomicCas32
	OpMIPS64LoweredAtomicCas64
	OpMIPS64LoweredNilCheck
	OpMIPS64FPFlagTrue
	OpMIPS64FPFlagFalse
	OpMIPS64LoweredGetClosurePtr
	OpMIPS64LoweredGetCallerSP
	OpMIPS64LoweredGetCallerPC
	OpMIPS64LoweredWB
	OpMIPS64LoweredPubBarrier
	OpMIPS64LoweredPanicBoundsRR
	OpMIPS64LoweredPanicBoundsRC
	OpMIPS64LoweredPanicBoundsCR
	OpMIPS64LoweredPanicBoundsCC

	OpPPC64ADD
	OpPPC64ADDCC
	OpPPC64ADDconst
	OpPPC64ADDCCconst
	OpPPC64FADD
	OpPPC64FADDS
	OpPPC64SUB
	OpPPC64SUBCC
	OpPPC64SUBFCconst
	OpPPC64FSUB
	OpPPC64FSUBS
	OpPPC64XSMINJDP
	OpPPC64XSMAXJDP
	OpPPC64MULLD
	OpPPC64MULLW
	OpPPC64MULLDconst
	OpPPC64MULLWconst
	OpPPC64MADDLD
	OpPPC64MULHD
	OpPPC64MULHW
	OpPPC64MULHDU
	OpPPC64MULHDUCC
	OpPPC64MULHWU
	OpPPC64FMUL
	OpPPC64FMULS
	OpPPC64FMADD
	OpPPC64FMADDS
	OpPPC64FMSUB
	OpPPC64FMSUBS
	OpPPC64SRAD
	OpPPC64SRAW
	OpPPC64SRD
	OpPPC64SRW
	OpPPC64SLD
	OpPPC64SLW
	OpPPC64ROTL
	OpPPC64ROTLW
	OpPPC64CLRLSLWI
	OpPPC64CLRLSLDI
	OpPPC64ADDC
	OpPPC64SUBC
	OpPPC64ADDCconst
	OpPPC64SUBCconst
	OpPPC64ADDE
	OpPPC64ADDZE
	OpPPC64SUBE
	OpPPC64ADDZEzero
	OpPPC64SUBZEzero
	OpPPC64SRADconst
	OpPPC64SRAWconst
	OpPPC64SRDconst
	OpPPC64SRWconst
	OpPPC64SLDconst
	OpPPC64SLWconst
	OpPPC64ROTLconst
	OpPPC64ROTLWconst
	OpPPC64EXTSWSLconst
	OpPPC64RLWINM
	OpPPC64RLWNM
	OpPPC64RLWMI
	OpPPC64RLDICL
	OpPPC64RLDICLCC
	OpPPC64RLDICR
	OpPPC64CNTLZD
	OpPPC64CNTLZDCC
	OpPPC64CNTLZW
	OpPPC64CNTTZD
	OpPPC64CNTTZW
	OpPPC64POPCNTD
	OpPPC64POPCNTW
	OpPPC64POPCNTB
	OpPPC64FDIV
	OpPPC64FDIVS
	OpPPC64DIVD
	OpPPC64DIVW
	OpPPC64DIVDU
	OpPPC64DIVWU
	OpPPC64MODUD
	OpPPC64MODSD
	OpPPC64MODUW
	OpPPC64MODSW
	OpPPC64FCTIDZ
	OpPPC64FCTIWZ
	OpPPC64FCFID
	OpPPC64FCFIDS
	OpPPC64FRSP
	OpPPC64MFVSRD
	OpPPC64MTVSRD
	OpPPC64AND
	OpPPC64ANDN
	OpPPC64ANDNCC
	OpPPC64ANDCC
	OpPPC64OR
	OpPPC64ORN
	OpPPC64ORCC
	OpPPC64NOR
	OpPPC64NORCC
	OpPPC64XOR
	OpPPC64XORCC
	OpPPC64EQV
	OpPPC64NEG
	OpPPC64NEGCC
	OpPPC64BRD
	OpPPC64BRW
	OpPPC64BRH
	OpPPC64FNEG
	OpPPC64FSQRT
	OpPPC64FSQRTS
	OpPPC64FFLOOR
	OpPPC64FCEIL
	OpPPC64FTRUNC
	OpPPC64FROUND
	OpPPC64FABS
	OpPPC64FNABS
	OpPPC64FCPSGN
	OpPPC64ORconst
	OpPPC64XORconst
	OpPPC64ANDCCconst
	OpPPC64ANDconst
	OpPPC64MOVBreg
	OpPPC64MOVBZreg
	OpPPC64MOVHreg
	OpPPC64MOVHZreg
	OpPPC64MOVWreg
	OpPPC64MOVWZreg
	OpPPC64MOVBZload
	OpPPC64MOVHload
	OpPPC64MOVHZload
	OpPPC64MOVWload
	OpPPC64MOVWZload
	OpPPC64MOVDload
	OpPPC64MOVDBRload
	OpPPC64MOVWBRload
	OpPPC64MOVHBRload
	OpPPC64MOVBZloadidx
	OpPPC64MOVHloadidx
	OpPPC64MOVHZloadidx
	OpPPC64MOVWloadidx
	OpPPC64MOVWZloadidx
	OpPPC64MOVDloadidx
	OpPPC64MOVHBRloadidx
	OpPPC64MOVWBRloadidx
	OpPPC64MOVDBRloadidx
	OpPPC64FMOVDloadidx
	OpPPC64FMOVSloadidx
	OpPPC64DCBT
	OpPPC64MOVDBRstore
	OpPPC64MOVWBRstore
	OpPPC64MOVHBRstore
	OpPPC64FMOVDload
	OpPPC64FMOVSload
	OpPPC64MOVBstore
	OpPPC64MOVHstore
	OpPPC64MOVWstore
	OpPPC64MOVDstore
	OpPPC64FMOVDstore
	OpPPC64FMOVSstore
	OpPPC64MOVBstoreidx
	OpPPC64MOVHstoreidx
	OpPPC64MOVWstoreidx
	OpPPC64MOVDstoreidx
	OpPPC64FMOVDstoreidx
	OpPPC64FMOVSstoreidx
	OpPPC64MOVHBRstoreidx
	OpPPC64MOVWBRstoreidx
	OpPPC64MOVDBRstoreidx
	OpPPC64MOVBstorezero
	OpPPC64MOVHstorezero
	OpPPC64MOVWstorezero
	OpPPC64MOVDstorezero
	OpPPC64MOVDaddr
	OpPPC64MOVDconst
	OpPPC64FMOVDconst
	OpPPC64FMOVSconst
	OpPPC64FCMPU
	OpPPC64CMP
	OpPPC64CMPU
	OpPPC64CMPW
	OpPPC64CMPWU
	OpPPC64CMPconst
	OpPPC64CMPUconst
	OpPPC64CMPWconst
	OpPPC64CMPWUconst
	OpPPC64ISEL
	OpPPC64ISELZ
	OpPPC64SETBC
	OpPPC64SETBCR
	OpPPC64Equal
	OpPPC64NotEqual
	OpPPC64LessThan
	OpPPC64FLessThan
	OpPPC64LessEqual
	OpPPC64FLessEqual
	OpPPC64GreaterThan
	OpPPC64FGreaterThan
	OpPPC64GreaterEqual
	OpPPC64FGreaterEqual
	OpPPC64LoweredGetClosurePtr
	OpPPC64LoweredGetCallerSP
	OpPPC64LoweredGetCallerPC
	OpPPC64LoweredNilCheck
	OpPPC64LoweredRound32F
	OpPPC64LoweredRound64F
	OpPPC64CALLstatic
	OpPPC64CALLtail
	OpPPC64CALLtailinter
	OpPPC64CALLclosure
	OpPPC64CALLinter
	OpPPC64LoweredZero
	OpPPC64LoweredZeroShort
	OpPPC64LoweredQuadZeroShort
	OpPPC64LoweredQuadZero
	OpPPC64LoweredMove
	OpPPC64LoweredMoveShort
	OpPPC64LoweredQuadMove
	OpPPC64LoweredQuadMoveShort
	OpPPC64LoweredAtomicStore8
	OpPPC64LoweredAtomicStore32
	OpPPC64LoweredAtomicStore64
	OpPPC64LoweredAtomicLoad8
	OpPPC64LoweredAtomicLoad32
	OpPPC64LoweredAtomicLoad64
	OpPPC64LoweredAtomicLoadPtr
	OpPPC64LoweredAtomicAdd32
	OpPPC64LoweredAtomicAdd64
	OpPPC64LoweredAtomicExchange8
	OpPPC64LoweredAtomicExchange32
	OpPPC64LoweredAtomicExchange64
	OpPPC64LoweredAtomicCas64
	OpPPC64LoweredAtomicCas32
	OpPPC64LoweredAtomicAnd8
	OpPPC64LoweredAtomicAnd32
	OpPPC64LoweredAtomicOr8
	OpPPC64LoweredAtomicOr32
	OpPPC64LoweredWB
	OpPPC64LoweredPubBarrier
	OpPPC64LoweredPanicBoundsRR
	OpPPC64LoweredPanicBoundsRC
	OpPPC64LoweredPanicBoundsCR
	OpPPC64LoweredPanicBoundsCC
	OpPPC64InvertFlags
	OpPPC64FlagEQ
	OpPPC64FlagLT
	OpPPC64FlagGT

	OpRISCV64ADD
	OpRISCV64ADDI
	OpRISCV64ADDIW
	OpRISCV64NEG
	OpRISCV64NEGW
	OpRISCV64SUB
	OpRISCV64SUBW
	OpRISCV64MUL
	OpRISCV64MULW
	OpRISCV64MULH
	OpRISCV64MULHU
	OpRISCV64LoweredMuluhilo
	OpRISCV64LoweredMuluover
	OpRISCV64DIV
	OpRISCV64DIVU
	OpRISCV64DIVW
	OpRISCV64DIVUW
	OpRISCV64REM
	OpRISCV64REMU
	OpRISCV64REMW
	OpRISCV64REMUW
	OpRISCV64MOVaddr
	OpRISCV64MOVDconst
	OpRISCV64FMOVDconst
	OpRISCV64FMOVFconst
	OpRISCV64MOVBload
	OpRISCV64MOVHload
	OpRISCV64MOVWload
	OpRISCV64MOVDload
	OpRISCV64MOVBUload
	OpRISCV64MOVHUload
	OpRISCV64MOVWUload
	OpRISCV64MOVBstore
	OpRISCV64MOVHstore
	OpRISCV64MOVWstore
	OpRISCV64MOVDstore
	OpRISCV64MOVBstorezero
	OpRISCV64MOVHstorezero
	OpRISCV64MOVWstorezero
	OpRISCV64MOVDstorezero
	OpRISCV64MOVBreg
	OpRISCV64MOVHreg
	OpRISCV64MOVWreg
	OpRISCV64MOVDreg
	OpRISCV64MOVBUreg
	OpRISCV64MOVHUreg
	OpRISCV64MOVWUreg
	OpRISCV64MOVDnop
	OpRISCV64SLL
	OpRISCV64SLLW
	OpRISCV64SRA
	OpRISCV64SRAW
	OpRISCV64SRL
	OpRISCV64SRLW
	OpRISCV64SLLI
	OpRISCV64SLLIW
	OpRISCV64SRAI
	OpRISCV64SRAIW
	OpRISCV64SRLI
	OpRISCV64SRLIW
	OpRISCV64SH1ADD
	OpRISCV64SH2ADD
	OpRISCV64SH3ADD
	OpRISCV64AND
	OpRISCV64ANDN
	OpRISCV64ANDI
	OpRISCV64CLZ
	OpRISCV64CLZW
	OpRISCV64CPOP
	OpRISCV64CPOPW
	OpRISCV64CTZ
	OpRISCV64CTZW
	OpRISCV64NOT
	OpRISCV64OR
	OpRISCV64ORN
	OpRISCV64ORI
	OpRISCV64REV8
	OpRISCV64ROL
	OpRISCV64ROLW
	OpRISCV64ROR
	OpRISCV64RORI
	OpRISCV64RORIW
	OpRISCV64RORW
	OpRISCV64XNOR
	OpRISCV64XOR
	OpRISCV64XORI
	OpRISCV64MIN
	OpRISCV64MAX
	OpRISCV64MINU
	OpRISCV64MAXU
	OpRISCV64SEQZ
	OpRISCV64SNEZ
	OpRISCV64SLT
	OpRISCV64SLTI
	OpRISCV64SLTU
	OpRISCV64SLTIU
	OpRISCV64LoweredRound32F
	OpRISCV64LoweredRound64F
	OpRISCV64CALLstatic
	OpRISCV64CALLtail
	OpRISCV64CALLtailinter
	OpRISCV64CALLclosure
	OpRISCV64CALLinter
	OpRISCV64LoweredZero
	OpRISCV64LoweredZeroLoop
	OpRISCV64LoweredMove
	OpRISCV64LoweredMoveLoop
	OpRISCV64LoweredAtomicLoad8
	OpRISCV64LoweredAtomicLoad32
	OpRISCV64LoweredAtomicLoad64
	OpRISCV64LoweredAtomicStore8
	OpRISCV64LoweredAtomicStore32
	OpRISCV64LoweredAtomicStore64
	OpRISCV64LoweredAtomicExchange32
	OpRISCV64LoweredAtomicExchange64
	OpRISCV64LoweredAtomicAdd32
	OpRISCV64LoweredAtomicAdd64
	OpRISCV64LoweredAtomicCas32
	OpRISCV64LoweredAtomicCas64
	OpRISCV64LoweredAtomicAnd32
	OpRISCV64LoweredAtomicOr32
	OpRISCV64LoweredNilCheck
	OpRISCV64LoweredGetClosurePtr
	OpRISCV64LoweredGetCallerSP
	OpRISCV64LoweredGetCallerPC
	OpRISCV64LoweredWB
	OpRISCV64LoweredPubBarrier
	OpRISCV64LoweredPanicBoundsRR
	OpRISCV64LoweredPanicBoundsRC
	OpRISCV64LoweredPanicBoundsCR
	OpRISCV64LoweredPanicBoundsCC
	OpRISCV64FADDS
	OpRISCV64FSUBS
	OpRISCV64FMULS
	OpRISCV64FDIVS
	OpRISCV64FMADDS
	OpRISCV64FMSUBS
	OpRISCV64FNMADDS
	OpRISCV64FNMSUBS
	OpRISCV64FSQRTS
	OpRISCV64FABSS
	OpRISCV64FNEGS
	OpRISCV64FMVSX
	OpRISCV64FMVXS
	OpRISCV64FCVTSW
	OpRISCV64FCVTSL
	OpRISCV64FCVTWS
	OpRISCV64FCVTLS
	OpRISCV64FMOVWload
	OpRISCV64FMOVWstore
	OpRISCV64FEQS
	OpRISCV64FNES
	OpRISCV64FLTS
	OpRISCV64FLES
	OpRISCV64LoweredFMAXS
	OpRISCV64LoweredFMINS
	OpRISCV64FADDD
	OpRISCV64FSUBD
	OpRISCV64FMULD
	OpRISCV64FDIVD
	OpRISCV64FMADDD
	OpRISCV64FMSUBD
	OpRISCV64FNMADDD
	OpRISCV64FNMSUBD
	OpRISCV64FSQRTD
	OpRISCV64FNEGD
	OpRISCV64FABSD
	OpRISCV64FSGNJD
	OpRISCV64FMVDX
	OpRISCV64FMVXD
	OpRISCV64FCVTDW
	OpRISCV64FCVTDL
	OpRISCV64FCVTWD
	OpRISCV64FCVTLD
	OpRISCV64FCVTDS
	OpRISCV64FCVTSD
	OpRISCV64FMOVDload
	OpRISCV64FMOVDstore
	OpRISCV64FEQD
	OpRISCV64FNED
	OpRISCV64FLTD
	OpRISCV64FLED
	OpRISCV64LoweredFMIND
	OpRISCV64LoweredFMAXD
	OpRISCV64FCLASSS
	OpRISCV64FCLASSD
	OpRISCV64CZEROEQZ
	OpRISCV64CZERONEZ

	OpS390XFADDS
	OpS390XFADD
	OpS390XFSUBS
	OpS390XFSUB
	OpS390XFMULS
	OpS390XFMUL
	OpS390XFDIVS
	OpS390XFDIV
	OpS390XFNEGS
	OpS390XFNEG
	OpS390XFMADDS
	OpS390XFMADD
	OpS390XFMSUBS
	OpS390XFMSUB
	OpS390XLPDFR
	OpS390XLNDFR
	OpS390XCPSDR
	OpS390XWFMAXDB
	OpS390XWFMAXSB
	OpS390XWFMINDB
	OpS390XWFMINSB
	OpS390XFIDBR
	OpS390XFMOVSload
	OpS390XFMOVDload
	OpS390XFMOVSconst
	OpS390XFMOVDconst
	OpS390XFMOVSloadidx
	OpS390XFMOVDloadidx
	OpS390XFMOVSstore
	OpS390XFMOVDstore
	OpS390XFMOVSstoreidx
	OpS390XFMOVDstoreidx
	OpS390XADD
	OpS390XADDW
	OpS390XADDconst
	OpS390XADDWconst
	OpS390XADDload
	OpS390XADDWload
	OpS390XSUB
	OpS390XSUBW
	OpS390XSUBconst
	OpS390XSUBWconst
	OpS390XSUBload
	OpS390XSUBWload
	OpS390XMULLD
	OpS390XMULLW
	OpS390XMULLDconst
	OpS390XMULLWconst
	OpS390XMULLDload
	OpS390XMULLWload
	OpS390XMULHD
	OpS390XMULHDU
	OpS390XDIVD
	OpS390XDIVW
	OpS390XDIVDU
	OpS390XDIVWU
	OpS390XMODD
	OpS390XMODW
	OpS390XMODDU
	OpS390XMODWU
	OpS390XAND
	OpS390XANDW
	OpS390XANDconst
	OpS390XANDWconst
	OpS390XANDload
	OpS390XANDWload
	OpS390XOR
	OpS390XORW
	OpS390XORconst
	OpS390XORWconst
	OpS390XORload
	OpS390XORWload
	OpS390XXOR
	OpS390XXORW
	OpS390XXORconst
	OpS390XXORWconst
	OpS390XXORload
	OpS390XXORWload
	OpS390XADDC
	OpS390XADDCconst
	OpS390XADDE
	OpS390XSUBC
	OpS390XSUBE
	OpS390XCMP
	OpS390XCMPW
	OpS390XCMPU
	OpS390XCMPWU
	OpS390XCMPconst
	OpS390XCMPWconst
	OpS390XCMPUconst
	OpS390XCMPWUconst
	OpS390XFCMPS
	OpS390XFCMP
	OpS390XLTDBR
	OpS390XLTEBR
	OpS390XSLD
	OpS390XSLW
	OpS390XSLDconst
	OpS390XSLWconst
	OpS390XSRD
	OpS390XSRW
	OpS390XSRDconst
	OpS390XSRWconst
	OpS390XSRAD
	OpS390XSRAW
	OpS390XSRADconst
	OpS390XSRAWconst
	OpS390XRLLG
	OpS390XRLL
	OpS390XRLLconst
	OpS390XRXSBG
	OpS390XRISBGZ
	OpS390XNEG
	OpS390XNEGW
	OpS390XNOT
	OpS390XNOTW
	OpS390XFSQRT
	OpS390XFSQRTS
	OpS390XLOCGR
	OpS390XMOVBreg
	OpS390XMOVBZreg
	OpS390XMOVHreg
	OpS390XMOVHZreg
	OpS390XMOVWreg
	OpS390XMOVWZreg
	OpS390XMOVDconst
	OpS390XLDGR
	OpS390XLGDR
	OpS390XCFDBRA
	OpS390XCGDBRA
	OpS390XCFEBRA
	OpS390XCGEBRA
	OpS390XCEFBRA
	OpS390XCDFBRA
	OpS390XCEGBRA
	OpS390XCDGBRA
	OpS390XCLFEBR
	OpS390XCLFDBR
	OpS390XCLGEBR
	OpS390XCLGDBR
	OpS390XCELFBR
	OpS390XCDLFBR
	OpS390XCELGBR
	OpS390XCDLGBR
	OpS390XLEDBR
	OpS390XLDEBR
	OpS390XMOVDaddr
	OpS390XMOVDaddridx
	OpS390XMOVBZload
	OpS390XMOVBload
	OpS390XMOVHZload
	OpS390XMOVHload
	OpS390XMOVWZload
	OpS390XMOVWload
	OpS390XMOVDload
	OpS390XMOVWBR
	OpS390XMOVDBR
	OpS390XMOVHBRload
	OpS390XMOVWBRload
	OpS390XMOVDBRload
	OpS390XMOVBstore
	OpS390XMOVHstore
	OpS390XMOVWstore
	OpS390XMOVDstore
	OpS390XMOVHBRstore
	OpS390XMOVWBRstore
	OpS390XMOVDBRstore
	OpS390XMVC
	OpS390XMOVBZloadidx
	OpS390XMOVBloadidx
	OpS390XMOVHZloadidx
	OpS390XMOVHloadidx
	OpS390XMOVWZloadidx
	OpS390XMOVWloadidx
	OpS390XMOVDloadidx
	OpS390XMOVHBRloadidx
	OpS390XMOVWBRloadidx
	OpS390XMOVDBRloadidx
	OpS390XMOVBstoreidx
	OpS390XMOVHstoreidx
	OpS390XMOVWstoreidx
	OpS390XMOVDstoreidx
	OpS390XMOVHBRstoreidx
	OpS390XMOVWBRstoreidx
	OpS390XMOVDBRstoreidx
	OpS390XMOVBstoreconst
	OpS390XMOVHstoreconst
	OpS390XMOVWstoreconst
	OpS390XMOVDstoreconst
	OpS390XCLEAR
	OpS390XCALLstatic
	OpS390XCALLtail
	OpS390XCALLtailinter
	OpS390XCALLclosure
	OpS390XCALLinter
	OpS390XInvertFlags
	OpS390XLoweredGetG
	OpS390XLoweredGetClosurePtr
	OpS390XLoweredGetCallerSP
	OpS390XLoweredGetCallerPC
	OpS390XLoweredNilCheck
	OpS390XLoweredRound32F
	OpS390XLoweredRound64F
	OpS390XLoweredWB
	OpS390XLoweredPanicBoundsRR
	OpS390XLoweredPanicBoundsRC
	OpS390XLoweredPanicBoundsCR
	OpS390XLoweredPanicBoundsCC
	OpS390XFlagEQ
	OpS390XFlagLT
	OpS390XFlagGT
	OpS390XFlagOV
	OpS390XSYNC
	OpS390XMOVBZatomicload
	OpS390XMOVWZatomicload
	OpS390XMOVDatomicload
	OpS390XMOVBatomicstore
	OpS390XMOVWatomicstore
	OpS390XMOVDatomicstore
	OpS390XLAA
	OpS390XLAAG
	OpS390XAddTupleFirst32
	OpS390XAddTupleFirst64
	OpS390XLAN
	OpS390XLANfloor
	OpS390XLAO
	OpS390XLAOfloor
	OpS390XLoweredAtomicCas32
	OpS390XLoweredAtomicCas64
	OpS390XLoweredAtomicExchange32
	OpS390XLoweredAtomicExchange64
	OpS390XFLOGR
	OpS390XPOPCNT
	OpS390XMLGR
	OpS390XSumBytes2
	OpS390XSumBytes4
	OpS390XSumBytes8
	OpS390XSTMG2
	OpS390XSTMG3
	OpS390XSTMG4
	OpS390XSTM2
	OpS390XSTM3
	OpS390XSTM4
	OpS390XLoweredMove
	OpS390XLoweredZero

	OpWasmLoweredStaticCall
	OpWasmLoweredTailCall
	OpWasmLoweredTailCallInter
	OpWasmLoweredClosureCall
	OpWasmLoweredInterCall
	OpWasmLoweredAddr
	OpWasmLoweredMove
	OpWasmLoweredZero
	OpWasmLoweredGetClosurePtr
	OpWasmLoweredGetCallerPC
	OpWasmLoweredGetCallerSP
	OpWasmLoweredNilCheck
	OpWasmLoweredWB
	OpWasmLoweredConvert
	OpWasmSelect
	OpWasmSelectV
	OpWasmI64Load8U
	OpWasmI64Load8S
	OpWasmI64Load16U
	OpWasmI64Load16S
	OpWasmI64Load32U
	OpWasmI64Load32S
	OpWasmI64Load
	OpWasmI64Store8
	OpWasmI64Store16
	OpWasmI64Store32
	OpWasmI64Store
	OpWasmF32Load
	OpWasmF64Load
	OpWasmF32Store
	OpWasmF64Store
	OpWasmI64Const
	OpWasmF32Const
	OpWasmF64Const
	OpWasmV128Load
	OpWasmV128Store
	OpWasmV128Zero
	OpWasmI64Eqz
	OpWasmI64Eq
	OpWasmI64Ne
	OpWasmI64LtS
	OpWasmI64LtU
	OpWasmI64GtS
	OpWasmI64GtU
	OpWasmI64LeS
	OpWasmI64LeU
	OpWasmI64GeS
	OpWasmI64GeU
	OpWasmF32Eq
	OpWasmF32Ne
	OpWasmF32Lt
	OpWasmF32Gt
	OpWasmF32Le
	OpWasmF32Ge
	OpWasmF64Eq
	OpWasmF64Ne
	OpWasmF64Lt
	OpWasmF64Gt
	OpWasmF64Le
	OpWasmF64Ge
	OpWasmI64Add
	OpWasmI64AddConst
	OpWasmI64Sub
	OpWasmI64Mul
	OpWasmI64DivS
	OpWasmI64DivU
	OpWasmI64RemS
	OpWasmI64RemU
	OpWasmI64And
	OpWasmI64Or
	OpWasmI64Xor
	OpWasmI64Shl
	OpWasmI64ShrS
	OpWasmI64ShrU
	OpWasmF32Neg
	OpWasmF32Add
	OpWasmF32Sub
	OpWasmF32Mul
	OpWasmF32Div
	OpWasmF64Neg
	OpWasmF64Add
	OpWasmF64Sub
	OpWasmF64Mul
	OpWasmF64Div
	OpWasmI64TruncSatF64S
	OpWasmI64TruncSatF64U
	OpWasmI64TruncSatF32S
	OpWasmI64TruncSatF32U
	OpWasmF32ConvertI64S
	OpWasmF32ConvertI64U
	OpWasmF64ConvertI64S
	OpWasmF64ConvertI64U
	OpWasmF32DemoteF64
	OpWasmF64PromoteF32
	OpWasmI64Extend8S
	OpWasmI64Extend16S
	OpWasmI64Extend32S
	OpWasmF32Sqrt
	OpWasmF32Trunc
	OpWasmF32Ceil
	OpWasmF32Floor
	OpWasmF32Nearest
	OpWasmF32Abs
	OpWasmF32Copysign
	OpWasmF64Sqrt
	OpWasmF64Trunc
	OpWasmF64Ceil
	OpWasmF64Floor
	OpWasmF64Nearest
	OpWasmF64Abs
	OpWasmF64Copysign
	OpWasmI64Ctz
	OpWasmI64Clz
	OpWasmI32Rotl
	OpWasmI64Rotl
	OpWasmI64Popcnt
	OpWasmI8x16AllTrue
	OpWasmV128AnyTrue
	OpWasmI16x8AllTrue
	OpWasmI16x8Q15MulrSatS
	OpWasmI16x8RelaxedQ15MulrS
	OpWasmI32x4AllTrue
	OpWasmF32x4Pmax
	OpWasmF32x4Pmin
	OpWasmF32x4RelaxedMax
	OpWasmF32x4RelaxedMin
	OpWasmI64x2AllTrue
	OpWasmF64x2Pmax
	OpWasmF64x2Pmin
	OpWasmF64x2RelaxedMax
	OpWasmF64x2RelaxedMin
	OpWasmI8x16Abs
	OpWasmI16x8Abs
	OpWasmI32x4Abs
	OpWasmF32x4Abs
	OpWasmI64x2Abs
	OpWasmF64x2Abs
	OpWasmI8x16Add
	OpWasmI16x8Add
	OpWasmI32x4Add
	OpWasmF32x4Add
	OpWasmI64x2Add
	OpWasmF64x2Add
	OpWasmI8x16AddSatS
	OpWasmI8x16AddSatU
	OpWasmI16x8AddSatS
	OpWasmI16x8AddSatU
	OpWasmV128And
	OpWasmV128Andnot
	OpWasmI8x16AvgrU
	OpWasmI16x8AvgrU
	OpWasmV128Bitselect
	OpWasmI8x16Splat
	OpWasmI16x8Splat
	OpWasmI32x4Splat
	OpWasmF32x4Splat
	OpWasmI64x2Splat
	OpWasmF64x2Splat
	OpWasmF32x4Ceil
	OpWasmF64x2Ceil
	OpWasmF64x2ConvertLowI32x4S
	OpWasmF64x2ConvertLowI32x4U
	OpWasmF32x4ConvertI32x4S
	OpWasmF32x4ConvertI32x4U
	OpWasmI32x4TruncSatF32x4S
	OpWasmI32x4TruncSatF32x4U
	OpWasmF32x4Div
	OpWasmF64x2Div
	OpWasmI8x16Eq
	OpWasmI16x8Eq
	OpWasmI32x4Eq
	OpWasmF32x4Eq
	OpWasmI64x2Eq
	OpWasmF64x2Eq
	OpWasmI64x2ExtendHighI32x4S
	OpWasmI64x2ExtendHighI32x4U
	OpWasmI32x4ExtendHighI16x8S
	OpWasmI32x4ExtendHighI16x8U
	OpWasmI16x8ExtendHighI8x16S
	OpWasmI16x8ExtendHighI8x16U
	OpWasmI64x2ExtendLowI32x4S
	OpWasmI64x2ExtendLowI32x4U
	OpWasmI32x4ExtendLowI16x8S
	OpWasmI32x4ExtendLowI16x8U
	OpWasmI16x8ExtendLowI8x16S
	OpWasmI16x8ExtendLowI8x16U
	OpWasmF32x4Floor
	OpWasmF64x2Floor
	OpWasmI8x16ExtractLaneS
	OpWasmI8x16ExtractLaneU
	OpWasmI16x8ExtractLaneS
	OpWasmI16x8ExtractLaneU
	OpWasmI32x4ExtractLane
	OpWasmF32x4ExtractLane
	OpWasmI64x2ExtractLane
	OpWasmF64x2ExtractLane
	OpWasmI8x16GtS
	OpWasmI8x16GtU
	OpWasmI16x8GtS
	OpWasmI16x8GtU
	OpWasmI32x4GtS
	OpWasmI32x4GtU
	OpWasmF32x4Gt
	OpWasmI64x2GtS
	OpWasmF64x2Gt
	OpWasmI8x16GeS
	OpWasmI8x16GeU
	OpWasmI16x8GeS
	OpWasmI16x8GeU
	OpWasmI32x4GeS
	OpWasmI32x4GeU
	OpWasmF32x4Ge
	OpWasmI64x2GeS
	OpWasmF64x2Ge
	OpWasmI8x16LtS
	OpWasmI8x16LtU
	OpWasmI16x8LtS
	OpWasmI16x8LtU
	OpWasmI32x4LtS
	OpWasmI32x4LtU
	OpWasmF32x4Lt
	OpWasmI64x2LtS
	OpWasmF64x2Lt
	OpWasmI8x16LeS
	OpWasmI8x16LeU
	OpWasmI16x8LeS
	OpWasmI16x8LeU
	OpWasmI32x4LeS
	OpWasmI32x4LeU
	OpWasmF32x4Le
	OpWasmI64x2LeS
	OpWasmF64x2Le
	OpWasmI8x16Swizzle
	OpWasmI8x16MaxS
	OpWasmI8x16MaxU
	OpWasmI16x8MaxS
	OpWasmI16x8MaxU
	OpWasmI32x4MaxS
	OpWasmI32x4MaxU
	OpWasmF32x4Max
	OpWasmF64x2Max
	OpWasmI8x16MinS
	OpWasmI8x16MinU
	OpWasmI16x8MinS
	OpWasmI16x8MinU
	OpWasmI32x4MinS
	OpWasmI32x4MinU
	OpWasmF32x4Min
	OpWasmF64x2Min
	OpWasmI16x8Mul
	OpWasmI32x4Mul
	OpWasmF32x4Mul
	OpWasmI64x2Mul
	OpWasmF64x2Mul
	OpWasmI16x8ExtmulHighI8x16S
	OpWasmI16x8ExtmulHighI8x16U
	OpWasmI32x4ExtmulHighI16x8S
	OpWasmI32x4ExtmulHighI16x8U
	OpWasmI64x2ExtmulHighI32x4S
	OpWasmI64x2ExtmulHighI32x4U
	OpWasmI16x8ExtmulLowI8x16S
	OpWasmI16x8ExtmulLowI8x16U
	OpWasmI32x4ExtmulLowI16x8S
	OpWasmI32x4ExtmulLowI16x8U
	OpWasmI64x2ExtmulLowI32x4S
	OpWasmI64x2ExtmulLowI32x4U
	OpWasmI8x16Neg
	OpWasmI16x8Neg
	OpWasmI32x4Neg
	OpWasmF32x4Neg
	OpWasmI64x2Neg
	OpWasmF64x2Neg
	OpWasmV128Not
	OpWasmI8x16Ne
	OpWasmI16x8Ne
	OpWasmI32x4Ne
	OpWasmF32x4Ne
	OpWasmI64x2Ne
	OpWasmF64x2Ne
	OpWasmI8x16Popcnt
	OpWasmV128Or
	OpWasmF32x4Nearest
	OpWasmF64x2Nearest
	OpWasmI8x16ReplaceLane
	OpWasmI16x8ReplaceLane
	OpWasmI32x4ReplaceLane
	OpWasmF32x4ReplaceLane
	OpWasmI64x2ReplaceLane
	OpWasmF64x2ReplaceLane
	OpWasmI8x16Shl
	OpWasmI16x8Shl
	OpWasmI32x4Shl
	OpWasmI64x2Shl
	OpWasmI8x16ShrS
	OpWasmI8x16ShrU
	OpWasmI16x8ShrS
	OpWasmI16x8ShrU
	OpWasmI32x4ShrS
	OpWasmI32x4ShrU
	OpWasmI64x2ShrS
	OpWasmI64x2ShrU
	OpWasmF32x4Sqrt
	OpWasmF64x2Sqrt
	OpWasmI8x16Sub
	OpWasmI16x8Sub
	OpWasmI32x4Sub
	OpWasmF32x4Sub
	OpWasmI64x2Sub
	OpWasmF64x2Sub
	OpWasmI8x16SubSatS
	OpWasmI8x16SubSatU
	OpWasmI16x8SubSatS
	OpWasmI16x8SubSatU
	OpWasmF32x4Trunc
	OpWasmF64x2Trunc
	OpWasmV128Xor

	OpLast
	OpAdd8
	OpAdd16
	OpAdd32
	OpAdd64
	OpAddPtr
	OpAdd32F
	OpAdd64F
	OpSub8
	OpSub16
	OpSub32
	OpSub64
	OpSubPtr
	OpSub32F
	OpSub64F
	OpMul8
	OpMul16
	OpMul32
	OpMul64
	OpMul32F
	OpMul64F
	OpDiv32F
	OpDiv64F
	OpHmul32
	OpHmul32u
	OpHmul64
	OpHmul64u
	OpMul32uhilo
	OpMul64uhilo
	OpMul32uover
	OpMul64uover
	OpAvg32u
	OpAvg64u
	OpDiv8
	OpDiv8u
	OpDiv16
	OpDiv16u
	OpDiv32
	OpDiv32u
	OpDiv64
	OpDiv64u
	OpDiv128u
	OpMod8
	OpMod8u
	OpMod16
	OpMod16u
	OpMod32
	OpMod32u
	OpMod64
	OpMod64u
	OpAnd8
	OpAnd16
	OpAnd32
	OpAnd64
	OpOr8
	OpOr16
	OpOr32
	OpOr64
	OpXor8
	OpXor16
	OpXor32
	OpXor64
	OpLsh8x8
	OpLsh8x16
	OpLsh8x32
	OpLsh8x64
	OpLsh16x8
	OpLsh16x16
	OpLsh16x32
	OpLsh16x64
	OpLsh32x8
	OpLsh32x16
	OpLsh32x32
	OpLsh32x64
	OpLsh64x8
	OpLsh64x16
	OpLsh64x32
	OpLsh64x64
	OpRsh8x8
	OpRsh8x16
	OpRsh8x32
	OpRsh8x64
	OpRsh16x8
	OpRsh16x16
	OpRsh16x32
	OpRsh16x64
	OpRsh32x8
	OpRsh32x16
	OpRsh32x32
	OpRsh32x64
	OpRsh64x8
	OpRsh64x16
	OpRsh64x32
	OpRsh64x64
	OpRsh8Ux8
	OpRsh8Ux16
	OpRsh8Ux32
	OpRsh8Ux64
	OpRsh16Ux8
	OpRsh16Ux16
	OpRsh16Ux32
	OpRsh16Ux64
	OpRsh32Ux8
	OpRsh32Ux16
	OpRsh32Ux32
	OpRsh32Ux64
	OpRsh64Ux8
	OpRsh64Ux16
	OpRsh64Ux32
	OpRsh64Ux64
	OpEq8
	OpEq16
	OpEq32
	OpEq64
	OpEqPtr
	OpEqInter
	OpEqSlice
	OpEq32F
	OpEq64F
	OpNeq8
	OpNeq16
	OpNeq32
	OpNeq64
	OpNeqPtr
	OpNeqInter
	OpNeqSlice
	OpNeq32F
	OpNeq64F
	OpLess8
	OpLess8U
	OpLess16
	OpLess16U
	OpLess32
	OpLess32U
	OpLess64
	OpLess64U
	OpLess32F
	OpLess64F
	OpLeq8
	OpLeq8U
	OpLeq16
	OpLeq16U
	OpLeq32
	OpLeq32U
	OpLeq64
	OpLeq64U
	OpLeq32F
	OpLeq64F
	OpCondSelect
	OpAndB
	OpOrB
	OpEqB
	OpNeqB
	OpNot
	OpNeg8
	OpNeg16
	OpNeg32
	OpNeg64
	OpNeg32F
	OpNeg64F
	OpCom8
	OpCom16
	OpCom32
	OpCom64
	OpCtz8
	OpCtz16
	OpCtz32
	OpCtz64
	OpCtz64On32
	OpCtz8NonZero
	OpCtz16NonZero
	OpCtz32NonZero
	OpCtz64NonZero
	OpBitLen8
	OpBitLen16
	OpBitLen32
	OpBitLen64
	OpBswap16
	OpBswap32
	OpBswap64
	OpBitRev8
	OpBitRev16
	OpBitRev32
	OpBitRev64
	OpPopCount8
	OpPopCount16
	OpPopCount32
	OpPopCount64
	OpRotateLeft64
	OpRotateLeft32
	OpRotateLeft16
	OpRotateLeft8
	OpSqrt
	OpSqrt32
	OpFloor
	OpCeil
	OpTrunc
	OpRound
	OpRoundToEven
	OpAbs
	OpCopysign
	OpMin64
	OpMax64
	OpMin64u
	OpMax64u
	OpMin64F
	OpMin32F
	OpMax64F
	OpMax32F
	OpFMA
	OpPhi
	OpCopy
	OpConvert
	OpConstBool
	OpConstString
	OpConstNil
	OpConst8
	OpConst16
	OpConst32
	OpConst64
	OpConst32F
	OpConst64F
	OpConstInterface
	OpConstSlice
	OpInitMem
	OpArg
	OpArgIntReg
	OpArgFloatReg
	OpAddr
	OpLocalAddr
	OpSP
	OpSB
	OpSPanchored
	OpLoad
	OpDereference
	OpStore
	OpLoadMasked8
	OpLoadMasked16
	OpLoadMasked32
	OpLoadMasked64
	OpStoreMasked8
	OpStoreMasked16
	OpStoreMasked32
	OpStoreMasked64
	OpMove
	OpZero
	OpStoreWB
	OpMoveWB
	OpZeroWB
	OpWBend
	OpWB
	OpHasCPUFeature
	OpPanicBounds
	OpPanicExtend
	OpClosureCall
	OpStaticCall
	OpInterCall
	OpTailCall
	OpTailCallInter
	OpClosureLECall
	OpStaticLECall
	OpInterLECall
	OpTailLECall
	OpTailLECallInter
	OpSignExt8to16
	OpSignExt8to32
	OpSignExt8to64
	OpSignExt16to32
	OpSignExt16to64
	OpSignExt32to64
	OpZeroExt8to16
	OpZeroExt8to32
	OpZeroExt8to64
	OpZeroExt16to32
	OpZeroExt16to64
	OpZeroExt32to64
	OpTrunc16to8
	OpTrunc32to8
	OpTrunc32to16
	OpTrunc64to8
	OpTrunc64to16
	OpTrunc64to32
	OpCvt32to32F
	OpCvt32to64F
	OpCvt64to32F
	OpCvt64to64F
	OpCvt32Fto32
	OpCvt32Fto64
	OpCvt64Fto32
	OpCvt64Fto64
	OpCvt32Fto64F
	OpCvt64Fto32F
	OpCvtBoolToUint8
	OpRound32F
	OpRound64F
	OpIsNonNil
	OpIsInBounds
	OpIsSliceInBounds
	OpNilCheck
	OpGetG
	OpGetClosurePtr
	OpGetCallerPC
	OpGetCallerSP
	OpPtrIndex
	OpOffPtr
	OpSliceMake
	OpSlicePtr
	OpSliceLen
	OpSliceCap
	OpSlicePtrUnchecked
	OpComplexMake
	OpComplexReal
	OpComplexImag
	OpStringMake
	OpStringPtr
	OpStringLen
	OpIMake
	OpITab
	OpIData
	OpStructMake
	OpStructSelect
	OpArrayMake1
	OpArraySelect
	OpStoreReg
	OpLoadReg
	OpFwdRef
	OpUnknown
	OpVarDef
	OpVarLive
	OpKeepAlive
	OpInlMark
	OpInt64Make
	OpInt64Hi
	OpInt64Lo
	OpAdd32carry
	OpAdd32withcarry
	OpAdd32carrywithcarry
	OpSub32carry
	OpSub32withcarry
	OpAdd64carry
	OpSub64borrow
	OpSignmask
	OpZeromask
	OpSlicemask
	OpSpectreIndex
	OpSpectreSliceIndex
	OpCvt32Uto32F
	OpCvt32Uto64F
	OpCvt32Fto32U
	OpCvt64Fto32U
	OpCvt64Uto32F
	OpCvt64Uto64F
	OpCvt32Fto64U
	OpCvt64Fto64U
	OpSelect0
	OpSelect1
	OpMakeTuple
	OpSelectN
	OpSelectNAddr
	OpMakeResult
	OpAtomicLoad8
	OpAtomicLoad32
	OpAtomicLoad64
	OpAtomicLoadPtr
	OpAtomicLoadAcq32
	OpAtomicLoadAcq64
	OpAtomicStore8
	OpAtomicStore32
	OpAtomicStore64
	OpAtomicStorePtrNoWB
	OpAtomicStoreRel32
	OpAtomicStoreRel64
	OpAtomicExchange8
	OpAtomicExchange32
	OpAtomicExchange64
	OpAtomicAdd32
	OpAtomicAdd64
	OpAtomicCompareAndSwap32
	OpAtomicCompareAndSwap64
	OpAtomicCompareAndSwapRel32
	OpAtomicAnd8
	OpAtomicOr8
	OpAtomicAnd32
	OpAtomicOr32
	OpAtomicAnd64value
	OpAtomicAnd32value
	OpAtomicAnd8value
	OpAtomicOr64value
	OpAtomicOr32value
	OpAtomicOr8value
	OpAtomicStore8Variant
	OpAtomicStore32Variant
	OpAtomicStore64Variant
	OpAtomicAdd32Variant
	OpAtomicAdd64Variant
	OpAtomicExchange8Variant
	OpAtomicExchange32Variant
	OpAtomicExchange64Variant
	OpAtomicCompareAndSwap32Variant
	OpAtomicCompareAndSwap64Variant
	OpAtomicAnd64valueVariant
	OpAtomicOr64valueVariant
	OpAtomicAnd32valueVariant
	OpAtomicOr32valueVariant
	OpAtomicAnd8valueVariant
	OpAtomicOr8valueVariant
	OpPubBarrier
	OpClobber
	OpClobberReg
	OpPrefetchCache
	OpPrefetchCacheStreamed
	OpMemEq
	OpEmpty
	OpZeroSIMD
	OpCvt16toMask8x16
	OpCvt32toMask8x32
	OpCvt64toMask8x64
	OpCvt8toMask16x8
	OpCvt16toMask16x16
	OpCvt32toMask16x32
	OpCvt8toMask32x4
	OpCvt8toMask32x8
	OpCvt16toMask32x16
	OpCvt8toMask64x2
	OpCvt8toMask64x4
	OpCvt8toMask64x8
	OpCvtMask8x16to16
	OpCvtMask8x32to32
	OpCvtMask8x64to64
	OpCvtMask16x8to8
	OpCvtMask16x16to16
	OpCvtMask16x32to32
	OpCvtMask32x4to8
	OpCvtMask32x8to8
	OpCvtMask32x16to16
	OpCvtMask64x2to8
	OpCvtMask64x4to8
	OpCvtMask64x8to8
	OpIsZeroVec
	OpIsNaNFloat32x4
	OpIsNaNFloat32x8
	OpIsNaNFloat32x16
	OpIsNaNFloat64x2
	OpIsNaNFloat64x4
	OpIsNaNFloat64x8
	OpAESDecryptLastRoundUint8x16
	OpAESDecryptLastRoundUint8x32
	OpAESDecryptLastRoundUint8x64
	OpAESDecryptOneRoundUint8x16
	OpAESDecryptOneRoundUint8x32
	OpAESDecryptOneRoundUint8x64
	OpAESEncryptLastRoundUint8x16
	OpAESEncryptLastRoundUint8x32
	OpAESEncryptLastRoundUint8x64
	OpAESEncryptOneRoundUint8x16
	OpAESEncryptOneRoundUint8x32
	OpAESEncryptOneRoundUint8x64
	OpAESInvMixColumnsUint32x4
	OpAbsFloat32x4
	OpAbsFloat64x2
	OpAbsInt8x16
	OpAbsInt8x32
	OpAbsInt8x64
	OpAbsInt16x8
	OpAbsInt16x16
	OpAbsInt16x32
	OpAbsInt32x4
	OpAbsInt32x8
	OpAbsInt32x16
	OpAbsInt64x2
	OpAbsInt64x4
	OpAbsInt64x8
	OpAddFloat32x4
	OpAddFloat32x8
	OpAddFloat32x16
	OpAddFloat64x2
	OpAddFloat64x4
	OpAddFloat64x8
	OpAddInt8x16
	OpAddInt8x32
	OpAddInt8x64
	OpAddInt16x8
	OpAddInt16x16
	OpAddInt16x32
	OpAddInt32x4
	OpAddInt32x8
	OpAddInt32x16
	OpAddInt64x2
	OpAddInt64x4
	OpAddInt64x8
	OpAddOddSubEvenFloat32x4
	OpAddOddSubEvenFloat32x8
	OpAddOddSubEvenFloat64x2
	OpAddOddSubEvenFloat64x4
	OpAddSaturatedInt8x16
	OpAddSaturatedInt8x32
	OpAddSaturatedInt8x64
	OpAddSaturatedInt16x8
	OpAddSaturatedInt16x16
	OpAddSaturatedInt16x32
	OpAddSaturatedInt32x4
	OpAddSaturatedInt64x2
	OpAddSaturatedUint8x16
	OpAddSaturatedUint8x32
	OpAddSaturatedUint8x64
	OpAddSaturatedUint16x8
	OpAddSaturatedUint16x16
	OpAddSaturatedUint16x32
	OpAddSaturatedUint32x4
	OpAddSaturatedUint64x2
	OpAddUint8x16
	OpAddUint8x32
	OpAddUint8x64
	OpAddUint16x8
	OpAddUint16x16
	OpAddUint16x32
	OpAddUint32x4
	OpAddUint32x8
	OpAddUint32x16
	OpAddUint64x2
	OpAddUint64x4
	OpAddUint64x8
	OpAndInt8x16
	OpAndInt8x32
	OpAndInt8x64
	OpAndInt16x8
	OpAndInt16x16
	OpAndInt16x32
	OpAndInt32x4
	OpAndInt32x8
	OpAndInt32x16
	OpAndInt64x2
	OpAndInt64x4
	OpAndInt64x8
	OpAndNotInt8x16
	OpAndNotInt8x32
	OpAndNotInt8x64
	OpAndNotInt16x8
	OpAndNotInt16x16
	OpAndNotInt16x32
	OpAndNotInt32x4
	OpAndNotInt32x8
	OpAndNotInt32x16
	OpAndNotInt64x2
	OpAndNotInt64x4
	OpAndNotInt64x8
	OpAndNotUint8x16
	OpAndNotUint8x32
	OpAndNotUint8x64
	OpAndNotUint16x8
	OpAndNotUint16x16
	OpAndNotUint16x32
	OpAndNotUint32x4
	OpAndNotUint32x8
	OpAndNotUint32x16
	OpAndNotUint64x2
	OpAndNotUint64x4
	OpAndNotUint64x8
	OpAndUint8x16
	OpAndUint8x32
	OpAndUint8x64
	OpAndUint16x8
	OpAndUint16x16
	OpAndUint16x32
	OpAndUint32x4
	OpAndUint32x8
	OpAndUint32x16
	OpAndUint64x2
	OpAndUint64x4
	OpAndUint64x8
	OpAverageInt8x16
	OpAverageInt16x8
	OpAverageInt32x4
	OpAverageUint8x16
	OpAverageUint8x32
	OpAverageUint8x64
	OpAverageUint16x8
	OpAverageUint16x16
	OpAverageUint16x32
	OpAverageUint32x4
	OpBitSelectInt8x16
	OpBitSelectInt16x8
	OpBitSelectInt32x4
	OpBitSelectInt64x2
	OpBitSelectUint8x16
	OpBitSelectUint16x8
	OpBitSelectUint32x4
	OpBitSelectUint64x2
	OpBroadcastFloat32x4
	OpBroadcastFloat64x2
	OpBroadcastInt8x16
	OpBroadcastInt16x8
	OpBroadcastInt32x4
	OpBroadcastInt64x2
	OpCeilFloat32x4
	OpCeilFloat32x8
	OpCeilFloat64x2
	OpCeilFloat64x4
	OpCompressFloat32x4
	OpCompressFloat32x8
	OpCompressFloat32x16
	OpCompressFloat64x2
	OpCompressFloat64x4
	OpCompressFloat64x8
	OpCompressInt8x16
	OpCompressInt8x32
	OpCompressInt8x64
	OpCompressInt16x8
	OpCompressInt16x16
	OpCompressInt16x32
	OpCompressInt32x4
	OpCompressInt32x8
	OpCompressInt32x16
	OpCompressInt64x2
	OpCompressInt64x4
	OpCompressInt64x8
	OpCompressUint8x16
	OpCompressUint8x32
	OpCompressUint8x64
	OpCompressUint16x8
	OpCompressUint16x16
	OpCompressUint16x32
	OpCompressUint32x4
	OpCompressUint32x8
	OpCompressUint32x16
	OpCompressUint64x2
	OpCompressUint64x4
	OpCompressUint64x8
	OpConcatAddPairsFloat32x4
	OpConcatAddPairsFloat64x2
	OpConcatAddPairsGroupedFloat32x8
	OpConcatAddPairsGroupedFloat64x4
	OpConcatAddPairsGroupedInt16x16
	OpConcatAddPairsGroupedInt32x8
	OpConcatAddPairsGroupedUint16x16
	OpConcatAddPairsGroupedUint32x8
	OpConcatAddPairsInt16x8
	OpConcatAddPairsInt32x4
	OpConcatAddPairsInt64x2
	OpConcatAddPairsSaturatedGroupedInt16x16
	OpConcatAddPairsSaturatedInt16x8
	OpConcatAddPairsUint16x8
	OpConcatAddPairsUint32x4
	OpConcatAddPairsUint64x2
	OpConcatEvenInt8x16
	OpConcatEvenInt16x8
	OpConcatEvenInt32x4
	OpConcatEvenInt64x2
	OpConcatEvenUint8x16
	OpConcatEvenUint16x8
	OpConcatEvenUint32x4
	OpConcatEvenUint64x2
	OpConcatOddInt8x16
	OpConcatOddInt16x8
	OpConcatOddInt32x4
	OpConcatOddInt64x2
	OpConcatOddUint8x16
	OpConcatOddUint16x8
	OpConcatOddUint32x4
	OpConcatOddUint64x2
	OpConcatPermuteFloat32x4
	OpConcatPermuteFloat32x8
	OpConcatPermuteFloat32x16
	OpConcatPermuteFloat64x2
	OpConcatPermuteFloat64x4
	OpConcatPermuteFloat64x8
	OpConcatPermuteInt8x16
	OpConcatPermuteInt8x32
	OpConcatPermuteInt8x64
	OpConcatPermuteInt16x8
	OpConcatPermuteInt16x16
	OpConcatPermuteInt16x32
	OpConcatPermuteInt32x4
	OpConcatPermuteInt32x8
	OpConcatPermuteInt32x16
	OpConcatPermuteInt64x2
	OpConcatPermuteInt64x4
	OpConcatPermuteInt64x8
	OpConcatPermuteUint8x16
	OpConcatPermuteUint8x32
	OpConcatPermuteUint8x64
	OpConcatPermuteUint16x8
	OpConcatPermuteUint16x16
	OpConcatPermuteUint16x32
	OpConcatPermuteUint32x4
	OpConcatPermuteUint32x8
	OpConcatPermuteUint32x16
	OpConcatPermuteUint64x2
	OpConcatPermuteUint64x4
	OpConcatPermuteUint64x8
	OpConcatSubPairsFloat32x4
	OpConcatSubPairsFloat64x2
	OpConcatSubPairsGroupedFloat32x8
	OpConcatSubPairsGroupedFloat64x4
	OpConcatSubPairsGroupedInt16x16
	OpConcatSubPairsGroupedInt32x8
	OpConcatSubPairsGroupedUint16x16
	OpConcatSubPairsGroupedUint32x8
	OpConcatSubPairsInt16x8
	OpConcatSubPairsInt32x4
	OpConcatSubPairsSaturatedGroupedInt16x16
	OpConcatSubPairsSaturatedInt16x8
	OpConcatSubPairsUint16x8
	OpConcatSubPairsUint32x4
	OpConvertLo2ToFloat64Float32x4
	OpConvertLo2ToFloat64Int32x4
	OpConvertLo2ToFloat64Uint32x4
	OpConvertToFloat32Float64x2
	OpConvertToFloat32Float64x4
	OpConvertToFloat32Float64x8
	OpConvertToFloat32Int32x4
	OpConvertToFloat32Int32x8
	OpConvertToFloat32Int32x16
	OpConvertToFloat32Int64x2
	OpConvertToFloat32Int64x4
	OpConvertToFloat32Int64x8
	OpConvertToFloat32Uint32x4
	OpConvertToFloat32Uint32x8
	OpConvertToFloat32Uint32x16
	OpConvertToFloat32Uint64x2
	OpConvertToFloat32Uint64x4
	OpConvertToFloat32Uint64x8
	OpConvertToFloat64Float32x4
	OpConvertToFloat64Float32x8
	OpConvertToFloat64Int32x4
	OpConvertToFloat64Int32x8
	OpConvertToFloat64Int64x2
	OpConvertToFloat64Int64x4
	OpConvertToFloat64Int64x8
	OpConvertToFloat64Uint32x4
	OpConvertToFloat64Uint32x8
	OpConvertToFloat64Uint64x2
	OpConvertToFloat64Uint64x4
	OpConvertToFloat64Uint64x8
	OpConvertToInt32Float32x4
	OpConvertToInt32Float32x8
	OpConvertToInt32Float32x16
	OpConvertToInt32Float64x2
	OpConvertToInt32Float64x4
	OpConvertToInt32Float64x8
	OpConvertToInt64Float32x4
	OpConvertToInt64Float32x8
	OpConvertToInt64Float64x2
	OpConvertToInt64Float64x4
	OpConvertToInt64Float64x8
	OpConvertToUint32Float32x4
	OpConvertToUint32Float32x8
	OpConvertToUint32Float32x16
	OpConvertToUint32Float64x2
	OpConvertToUint32Float64x4
	OpConvertToUint32Float64x8
	OpConvertToUint64Float32x4
	OpConvertToUint64Float32x8
	OpConvertToUint64Float64x2
	OpConvertToUint64Float64x4
	OpConvertToUint64Float64x8
	OpDivFloat32x4
	OpDivFloat32x8
	OpDivFloat32x16
	OpDivFloat64x2
	OpDivFloat64x4
	OpDivFloat64x8
	OpDotProductPairsInt16x8
	OpDotProductPairsInt16x16
	OpDotProductPairsInt16x32
	OpDotProductPairsSaturatedUint8x16
	OpDotProductPairsSaturatedUint8x32
	OpDotProductPairsSaturatedUint8x64
	OpEqualFloat32x4
	OpEqualFloat32x8
	OpEqualFloat32x16
	OpEqualFloat64x2
	OpEqualFloat64x4
	OpEqualFloat64x8
	OpEqualInt8x16
	OpEqualInt8x32
	OpEqualInt8x64
	OpEqualInt16x8
	OpEqualInt16x16
	OpEqualInt16x32
	OpEqualInt32x4
	OpEqualInt32x8
	OpEqualInt32x16
	OpEqualInt64x2
	OpEqualInt64x4
	OpEqualInt64x8
	OpEqualUint8x16
	OpEqualUint8x32
	OpEqualUint8x64
	OpEqualUint16x8
	OpEqualUint16x16
	OpEqualUint16x32
	OpEqualUint32x4
	OpEqualUint32x8
	OpEqualUint32x16
	OpEqualUint64x2
	OpEqualUint64x4
	OpEqualUint64x8
	OpExpandFloat32x4
	OpExpandFloat32x8
	OpExpandFloat32x16
	OpExpandFloat64x2
	OpExpandFloat64x4
	OpExpandFloat64x8
	OpExpandInt8x16
	OpExpandInt8x32
	OpExpandInt8x64
	OpExpandInt16x8
	OpExpandInt16x16
	OpExpandInt16x32
	OpExpandInt32x4
	OpExpandInt32x8
	OpExpandInt32x16
	OpExpandInt64x2
	OpExpandInt64x4
	OpExpandInt64x8
	OpExpandUint8x16
	OpExpandUint8x32
	OpExpandUint8x64
	OpExpandUint16x8
	OpExpandUint16x16
	OpExpandUint16x32
	OpExpandUint32x4
	OpExpandUint32x8
	OpExpandUint32x16
	OpExpandUint64x2
	OpExpandUint64x4
	OpExpandUint64x8
	OpExtendHi2ToInt64Int32x4
	OpExtendHi2ToUint64Uint32x4
	OpExtendHi4ToInt32Int16x8
	OpExtendHi4ToUint32Uint16x8
	OpExtendHi8ToInt16Int8x16
	OpExtendHi8ToUint16Uint8x16
	OpExtendLo2ToInt64Int8x16
	OpExtendLo2ToInt64Int16x8
	OpExtendLo2ToInt64Int32x4
	OpExtendLo2ToUint64Uint8x16
	OpExtendLo2ToUint64Uint16x8
	OpExtendLo2ToUint64Uint32x4
	OpExtendLo4ToInt32Int8x16
	OpExtendLo4ToInt32Int16x8
	OpExtendLo4ToInt64Int8x16
	OpExtendLo4ToInt64Int16x8
	OpExtendLo4ToUint32Uint8x16
	OpExtendLo4ToUint32Uint16x8
	OpExtendLo4ToUint64Uint8x16
	OpExtendLo4ToUint64Uint16x8
	OpExtendLo8ToInt16Int8x16
	OpExtendLo8ToInt32Int8x16
	OpExtendLo8ToInt64Int8x16
	OpExtendLo8ToUint16Uint8x16
	OpExtendLo8ToUint32Uint8x16
	OpExtendLo8ToUint64Uint8x16
	OpExtendToInt16Int8x16
	OpExtendToInt16Int8x32
	OpExtendToInt32Int8x16
	OpExtendToInt32Int16x8
	OpExtendToInt32Int16x16
	OpExtendToInt64Int16x8
	OpExtendToInt64Int32x4
	OpExtendToInt64Int32x8
	OpExtendToUint16Uint8x16
	OpExtendToUint16Uint8x32
	OpExtendToUint32Uint8x16
	OpExtendToUint32Uint16x8
	OpExtendToUint32Uint16x16
	OpExtendToUint64Uint16x8
	OpExtendToUint64Uint32x4
	OpExtendToUint64Uint32x8
	OpFloorFloat32x4
	OpFloorFloat32x8
	OpFloorFloat64x2
	OpFloorFloat64x4
	OpGaloisFieldMulUint8x16
	OpGaloisFieldMulUint8x32
	OpGaloisFieldMulUint8x64
	OpGetHiFloat32x8
	OpGetHiFloat32x16
	OpGetHiFloat64x4
	OpGetHiFloat64x8
	OpGetHiInt8x32
	OpGetHiInt8x64
	OpGetHiInt16x16
	OpGetHiInt16x32
	OpGetHiInt32x8
	OpGetHiInt32x16
	OpGetHiInt64x4
	OpGetHiInt64x8
	OpGetHiUint8x32
	OpGetHiUint8x64
	OpGetHiUint16x16
	OpGetHiUint16x32
	OpGetHiUint32x8
	OpGetHiUint32x16
	OpGetHiUint64x4
	OpGetHiUint64x8
	OpGetLoFloat32x8
	OpGetLoFloat32x16
	OpGetLoFloat64x4
	OpGetLoFloat64x8
	OpGetLoInt8x32
	OpGetLoInt8x64
	OpGetLoInt16x16
	OpGetLoInt16x32
	OpGetLoInt32x8
	OpGetLoInt32x16
	OpGetLoInt64x4
	OpGetLoInt64x8
	OpGetLoUint8x32
	OpGetLoUint8x64
	OpGetLoUint16x16
	OpGetLoUint16x32
	OpGetLoUint32x8
	OpGetLoUint32x16
	OpGetLoUint64x4
	OpGetLoUint64x8
	OpGreaterEqualFloat32x4
	OpGreaterEqualFloat32x8
	OpGreaterEqualFloat32x16
	OpGreaterEqualFloat64x2
	OpGreaterEqualFloat64x4
	OpGreaterEqualFloat64x8
	OpGreaterEqualInt8x16
	OpGreaterEqualInt8x64
	OpGreaterEqualInt16x8
	OpGreaterEqualInt16x32
	OpGreaterEqualInt32x4
	OpGreaterEqualInt32x16
	OpGreaterEqualInt64x2
	OpGreaterEqualInt64x8
	OpGreaterEqualUint8x16
	OpGreaterEqualUint8x64
	OpGreaterEqualUint16x8
	OpGreaterEqualUint16x32
	OpGreaterEqualUint32x4
	OpGreaterEqualUint32x16
	OpGreaterEqualUint64x2
	OpGreaterEqualUint64x8
	OpGreaterFloat32x4
	OpGreaterFloat32x8
	OpGreaterFloat32x16
	OpGreaterFloat64x2
	OpGreaterFloat64x4
	OpGreaterFloat64x8
	OpGreaterInt8x16
	OpGreaterInt8x32
	OpGreaterInt8x64
	OpGreaterInt16x8
	OpGreaterInt16x16
	OpGreaterInt16x32
	OpGreaterInt32x4
	OpGreaterInt32x8
	OpGreaterInt32x16
	OpGreaterInt64x2
	OpGreaterInt64x4
	OpGreaterInt64x8
	OpGreaterUint8x16
	OpGreaterUint8x64
	OpGreaterUint16x8
	OpGreaterUint16x32
	OpGreaterUint32x4
	OpGreaterUint32x16
	OpGreaterUint64x2
	OpGreaterUint64x8
	OpInterleaveEvenInt8x16
	OpInterleaveEvenInt16x8
	OpInterleaveEvenInt32x4
	OpInterleaveEvenInt64x2
	OpInterleaveEvenUint8x16
	OpInterleaveEvenUint16x8
	OpInterleaveEvenUint32x4
	OpInterleaveEvenUint64x2
	OpInterleaveHiGroupedInt16x16
	OpInterleaveHiGroupedInt16x32
	OpInterleaveHiGroupedInt32x8
	OpInterleaveHiGroupedInt32x16
	OpInterleaveHiGroupedInt64x4
	OpInterleaveHiGroupedInt64x8
	OpInterleaveHiGroupedUint16x16
	OpInterleaveHiGroupedUint16x32
	OpInterleaveHiGroupedUint32x8
	OpInterleaveHiGroupedUint32x16
	OpInterleaveHiGroupedUint64x4
	OpInterleaveHiGroupedUint64x8
	OpInterleaveHiInt8x16
	OpInterleaveHiInt16x8
	OpInterleaveHiInt32x4
	OpInterleaveHiInt64x2
	OpInterleaveHiUint8x16
	OpInterleaveHiUint16x8
	OpInterleaveHiUint32x4
	OpInterleaveHiUint64x2
	OpInterleaveLoGroupedInt16x16
	OpInterleaveLoGroupedInt16x32
	OpInterleaveLoGroupedInt32x8
	OpInterleaveLoGroupedInt32x16
	OpInterleaveLoGroupedInt64x4
	OpInterleaveLoGroupedInt64x8
	OpInterleaveLoGroupedUint16x16
	OpInterleaveLoGroupedUint16x32
	OpInterleaveLoGroupedUint32x8
	OpInterleaveLoGroupedUint32x16
	OpInterleaveLoGroupedUint64x4
	OpInterleaveLoGroupedUint64x8
	OpInterleaveLoInt8x16
	OpInterleaveLoInt16x8
	OpInterleaveLoInt32x4
	OpInterleaveLoInt64x2
	OpInterleaveLoUint8x16
	OpInterleaveLoUint16x8
	OpInterleaveLoUint32x4
	OpInterleaveLoUint64x2
	OpInterleaveOddInt8x16
	OpInterleaveOddInt16x8
	OpInterleaveOddInt32x4
	OpInterleaveOddInt64x2
	OpInterleaveOddUint8x16
	OpInterleaveOddUint16x8
	OpInterleaveOddUint32x4
	OpInterleaveOddUint64x2
	OpLeadingSignBitsInt8x16
	OpLeadingSignBitsInt16x8
	OpLeadingSignBitsInt32x4
	OpLeadingSignBitsUint8x16
	OpLeadingSignBitsUint16x8
	OpLeadingSignBitsUint32x4
	OpLeadingZerosInt8x16
	OpLeadingZerosInt16x8
	OpLeadingZerosInt32x4
	OpLeadingZerosInt32x8
	OpLeadingZerosInt32x16
	OpLeadingZerosInt64x2
	OpLeadingZerosInt64x4
	OpLeadingZerosInt64x8
	OpLeadingZerosUint8x16
	OpLeadingZerosUint16x8
	OpLeadingZerosUint32x4
	OpLeadingZerosUint32x8
	OpLeadingZerosUint32x16
	OpLeadingZerosUint64x2
	OpLeadingZerosUint64x4
	OpLeadingZerosUint64x8
	OpLessEqualFloat32x4
	OpLessEqualFloat32x8
	OpLessEqualFloat32x16
	OpLessEqualFloat64x2
	OpLessEqualFloat64x4
	OpLessEqualFloat64x8
	OpLessEqualInt8x16
	OpLessEqualInt8x64
	OpLessEqualInt16x8
	OpLessEqualInt16x32
	OpLessEqualInt32x4
	OpLessEqualInt32x16
	OpLessEqualInt64x2
	OpLessEqualInt64x8
	OpLessEqualUint8x16
	OpLessEqualUint8x64
	OpLessEqualUint16x8
	OpLessEqualUint16x32
	OpLessEqualUint32x4
	OpLessEqualUint32x16
	OpLessEqualUint64x8
	OpLessFloat32x4
	OpLessFloat32x8
	OpLessFloat32x16
	OpLessFloat64x2
	OpLessFloat64x4
	OpLessFloat64x8
	OpLessInt8x16
	OpLessInt8x64
	OpLessInt16x8
	OpLessInt16x32
	OpLessInt32x4
	OpLessInt32x16
	OpLessInt64x2
	OpLessInt64x8
	OpLessUint8x16
	OpLessUint8x64
	OpLessUint16x8
	OpLessUint16x32
	OpLessUint32x4
	OpLessUint32x16
	OpLessUint64x8
	OpLookupOrZeroInt8x16
	OpLookupOrZeroUint8x16
	OpMaxFloat32x4
	OpMaxFloat32x8
	OpMaxFloat32x16
	OpMaxFloat64x2
	OpMaxFloat64x4
	OpMaxFloat64x8
	OpMaxInt8x16
	OpMaxInt8x32
	OpMaxInt8x64
	OpMaxInt16x8
	OpMaxInt16x16
	OpMaxInt16x32
	OpMaxInt32x4
	OpMaxInt32x8
	OpMaxInt32x16
	OpMaxInt64x2
	OpMaxInt64x4
	OpMaxInt64x8
	OpMaxUint8x16
	OpMaxUint8x32
	OpMaxUint8x64
	OpMaxUint16x8
	OpMaxUint16x16
	OpMaxUint16x32
	OpMaxUint32x4
	OpMaxUint32x8
	OpMaxUint32x16
	OpMaxUint64x2
	OpMaxUint64x4
	OpMaxUint64x8
	OpMinFloat32x4
	OpMinFloat32x8
	OpMinFloat32x16
	OpMinFloat64x2
	OpMinFloat64x4
	OpMinFloat64x8
	OpMinInt8x16
	OpMinInt8x32
	OpMinInt8x64
	OpMinInt16x8
	OpMinInt16x16
	OpMinInt16x32
	OpMinInt32x4
	OpMinInt32x8
	OpMinInt32x16
	OpMinInt64x2
	OpMinInt64x4
	OpMinInt64x8
	OpMinUint8x16
	OpMinUint8x32
	OpMinUint8x64
	OpMinUint16x8
	OpMinUint16x16
	OpMinUint16x32
	OpMinUint32x4
	OpMinUint32x8
	OpMinUint32x16
	OpMinUint64x2
	OpMinUint64x4
	OpMinUint64x8
	OpMulAddEvenSubOddFloat32x4
	OpMulAddEvenSubOddFloat32x8
	OpMulAddEvenSubOddFloat32x16
	OpMulAddEvenSubOddFloat64x2
	OpMulAddEvenSubOddFloat64x4
	OpMulAddEvenSubOddFloat64x8
	OpMulAddFloat32x4
	OpMulAddFloat32x8
	OpMulAddFloat32x16
	OpMulAddFloat64x2
	OpMulAddFloat64x4
	OpMulAddFloat64x8
	OpMulAddInt8x16
	OpMulAddInt16x8
	OpMulAddInt32x4
	OpMulAddOddSubEvenFloat32x4
	OpMulAddOddSubEvenFloat32x8
	OpMulAddOddSubEvenFloat32x16
	OpMulAddOddSubEvenFloat64x2
	OpMulAddOddSubEvenFloat64x4
	OpMulAddOddSubEvenFloat64x8
	OpMulAddUint8x16
	OpMulAddUint16x8
	OpMulAddUint32x4
	OpMulFloat32x4
	OpMulFloat32x8
	OpMulFloat32x16
	OpMulFloat64x2
	OpMulFloat64x4
	OpMulFloat64x8
	OpMulHighInt16x8
	OpMulHighInt16x16
	OpMulHighInt16x32
	OpMulHighUint16x8
	OpMulHighUint16x16
	OpMulHighUint16x32
	OpMulInt8x16
	OpMulInt16x8
	OpMulInt16x16
	OpMulInt16x32
	OpMulInt32x4
	OpMulInt32x8
	OpMulInt32x16
	OpMulInt64x2
	OpMulInt64x4
	OpMulInt64x8
	OpMulSignInt8x16
	OpMulSignInt8x32
	OpMulSignInt16x8
	OpMulSignInt16x16
	OpMulSignInt32x4
	OpMulSignInt32x8
	OpMulUint8x16
	OpMulUint16x8
	OpMulUint16x16
	OpMulUint16x32
	OpMulUint32x4
	OpMulUint32x8
	OpMulUint32x16
	OpMulUint64x2
	OpMulUint64x4
	OpMulUint64x8
	OpMulWidenEvenInt32x4
	OpMulWidenEvenInt32x8
	OpMulWidenEvenUint32x4
	OpMulWidenEvenUint32x8
	OpMulWidenHiInt8x16
	OpMulWidenHiInt16x8
	OpMulWidenHiInt32x4
	OpMulWidenHiUint8x16
	OpMulWidenHiUint16x8
	OpMulWidenHiUint32x4
	OpMulWidenLoInt8x16
	OpMulWidenLoInt16x8
	OpMulWidenLoInt32x4
	OpMulWidenLoUint8x16
	OpMulWidenLoUint16x8
	OpMulWidenLoUint32x4
	OpNegFloat32x4
	OpNegFloat64x2
	OpNegInt8x16
	OpNegInt16x8
	OpNegInt32x4
	OpNegInt64x2
	OpNotEqualFloat32x4
	OpNotEqualFloat32x8
	OpNotEqualFloat32x16
	OpNotEqualFloat64x2
	OpNotEqualFloat64x4
	OpNotEqualFloat64x8
	OpNotEqualInt8x16
	OpNotEqualInt8x64
	OpNotEqualInt16x8
	OpNotEqualInt16x32
	OpNotEqualInt32x4
	OpNotEqualInt32x16
	OpNotEqualInt64x2
	OpNotEqualInt64x8
	OpNotEqualUint8x16
	OpNotEqualUint8x64
	OpNotEqualUint16x8
	OpNotEqualUint16x32
	OpNotEqualUint32x4
	OpNotEqualUint32x16
	OpNotEqualUint64x2
	OpNotEqualUint64x8
	OpNotInt8x16
	OpNotInt16x8
	OpNotInt32x4
	OpNotInt64x2
	OpNotUint8x16
	OpNotUint16x8
	OpNotUint32x4
	OpNotUint64x2
	OpOnesCountInt8x16
	OpOnesCountInt8x32
	OpOnesCountInt8x64
	OpOnesCountInt16x8
	OpOnesCountInt16x16
	OpOnesCountInt16x32
	OpOnesCountInt32x4
	OpOnesCountInt32x8
	OpOnesCountInt32x16
	OpOnesCountInt64x2
	OpOnesCountInt64x4
	OpOnesCountInt64x8
	OpOnesCountUint8x16
	OpOnesCountUint8x32
	OpOnesCountUint8x64
	OpOnesCountUint16x8
	OpOnesCountUint16x16
	OpOnesCountUint16x32
	OpOnesCountUint32x4
	OpOnesCountUint32x8
	OpOnesCountUint32x16
	OpOnesCountUint64x2
	OpOnesCountUint64x4
	OpOnesCountUint64x8
	OpOrInt8x16
	OpOrInt8x32
	OpOrInt8x64
	OpOrInt16x8
	OpOrInt16x16
	OpOrInt16x32
	OpOrInt32x4
	OpOrInt32x8
	OpOrInt32x16
	OpOrInt64x2
	OpOrInt64x4
	OpOrInt64x8
	OpOrNotInt8x16
	OpOrNotInt16x8
	OpOrNotInt32x4
	OpOrNotInt64x2
	OpOrNotUint8x16
	OpOrNotUint16x8
	OpOrNotUint32x4
	OpOrNotUint64x2
	OpOrUint8x16
	OpOrUint8x32
	OpOrUint8x64
	OpOrUint16x8
	OpOrUint16x16
	OpOrUint16x32
	OpOrUint32x4
	OpOrUint32x8
	OpOrUint32x16
	OpOrUint64x2
	OpOrUint64x4
	OpOrUint64x8
	OpPermuteFloat32x8
	OpPermuteFloat32x16
	OpPermuteFloat64x4
	OpPermuteFloat64x8
	OpPermuteInt8x16
	OpPermuteInt8x32
	OpPermuteInt8x64
	OpPermuteInt16x8
	OpPermuteInt16x16
	OpPermuteInt16x32
	OpPermuteInt32x8
	OpPermuteInt32x16
	OpPermuteInt64x4
	OpPermuteInt64x8
	OpPermuteOrZeroGroupedInt8x32
	OpPermuteOrZeroGroupedInt8x64
	OpPermuteOrZeroGroupedUint8x32
	OpPermuteOrZeroGroupedUint8x64
	OpPermuteOrZeroInt8x16
	OpPermuteOrZeroUint8x16
	OpPermuteUint8x16
	OpPermuteUint8x32
	OpPermuteUint8x64
	OpPermuteUint16x8
	OpPermuteUint16x16
	OpPermuteUint16x32
	OpPermuteUint32x8
	OpPermuteUint32x16
	OpPermuteUint64x4
	OpPermuteUint64x8
	OpReciprocalFloat32x4
	OpReciprocalFloat32x8
	OpReciprocalFloat32x16
	OpReciprocalFloat64x2
	OpReciprocalFloat64x4
	OpReciprocalFloat64x8
	OpReciprocalSqrtFloat32x4
	OpReciprocalSqrtFloat32x8
	OpReciprocalSqrtFloat32x16
	OpReciprocalSqrtFloat64x2
	OpReciprocalSqrtFloat64x4
	OpReciprocalSqrtFloat64x8
	OpRotateAllLeftVarInt8x16
	OpRotateAllLeftVarInt16x8
	OpRotateAllLeftVarInt32x4
	OpRotateAllLeftVarInt64x2
	OpRotateAllLeftVarUint8x16
	OpRotateAllLeftVarUint16x8
	OpRotateAllLeftVarUint32x4
	OpRotateAllLeftVarUint64x2
	OpRotateAllRightVarInt8x16
	OpRotateAllRightVarInt16x8
	OpRotateAllRightVarInt32x4
	OpRotateAllRightVarInt64x2
	OpRotateAllRightVarUint8x16
	OpRotateAllRightVarUint16x8
	OpRotateAllRightVarUint32x4
	OpRotateAllRightVarUint64x2
	OpRotateLeftInt32x4
	OpRotateLeftInt32x8
	OpRotateLeftInt32x16
	OpRotateLeftInt64x2
	OpRotateLeftInt64x4
	OpRotateLeftInt64x8
	OpRotateLeftUint32x4
	OpRotateLeftUint32x8
	OpRotateLeftUint32x16
	OpRotateLeftUint64x2
	OpRotateLeftUint64x4
	OpRotateLeftUint64x8
	OpRotateRightInt32x4
	OpRotateRightInt32x8
	OpRotateRightInt32x16
	OpRotateRightInt64x2
	OpRotateRightInt64x4
	OpRotateRightInt64x8
	OpRotateRightUint32x4
	OpRotateRightUint32x8
	OpRotateRightUint32x16
	OpRotateRightUint64x2
	OpRotateRightUint64x4
	OpRotateRightUint64x8
	OpRoundFloat32x4
	OpRoundFloat32x8
	OpRoundFloat64x2
	OpRoundFloat64x4
	OpSHA1Message1Uint32x4
	OpSHA1Message2Uint32x4
	OpSHA1NextEUint32x4
	OpSHA256Message1Uint32x4
	OpSHA256Message2Uint32x4
	OpSHA256TwoRoundsUint32x4
	OpSaturateToInt8Int16x8
	OpSaturateToInt8Int16x16
	OpSaturateToInt8Int16x32
	OpSaturateToInt8Int32x4
	OpSaturateToInt8Int32x8
	OpSaturateToInt8Int32x16
	OpSaturateToInt8Int64x2
	OpSaturateToInt8Int64x4
	OpSaturateToInt8Int64x8
	OpSaturateToInt16ConcatGroupedInt32x8
	OpSaturateToInt16ConcatGroupedInt32x16
	OpSaturateToInt16ConcatInt32x4
	OpSaturateToInt16Int32x4
	OpSaturateToInt16Int32x8
	OpSaturateToInt16Int32x16
	OpSaturateToInt16Int64x2
	OpSaturateToInt16Int64x4
	OpSaturateToInt16Int64x8
	OpSaturateToInt32Int64x2
	OpSaturateToInt32Int64x4
	OpSaturateToInt32Int64x8
	OpSaturateToUint8Int16x8
	OpSaturateToUint8Uint16x8
	OpSaturateToUint8Uint16x16
	OpSaturateToUint8Uint16x32
	OpSaturateToUint8Uint32x4
	OpSaturateToUint8Uint32x8
	OpSaturateToUint8Uint32x16
	OpSaturateToUint8Uint64x2
	OpSaturateToUint8Uint64x4
	OpSaturateToUint8Uint64x8
	OpSaturateToUint16ConcatGroupedInt32x8
	OpSaturateToUint16ConcatGroupedInt32x16
	OpSaturateToUint16ConcatInt32x4
	OpSaturateToUint16Int32x4
	OpSaturateToUint16Uint32x4
	OpSaturateToUint16Uint32x8
	OpSaturateToUint16Uint32x16
	OpSaturateToUint16Uint64x2
	OpSaturateToUint16Uint64x4
	OpSaturateToUint16Uint64x8
	OpSaturateToUint32Int64x2
	OpSaturateToUint32Uint64x2
	OpSaturateToUint32Uint64x4
	OpSaturateToUint32Uint64x8
	OpScaleFloat32x4
	OpScaleFloat32x8
	OpScaleFloat32x16
	OpScaleFloat64x2
	OpScaleFloat64x4
	OpScaleFloat64x8
	OpSetHiFloat32x8
	OpSetHiFloat32x16
	OpSetHiFloat64x4
	OpSetHiFloat64x8
	OpSetHiInt8x32
	OpSetHiInt8x64
	OpSetHiInt16x16
	OpSetHiInt16x32
	OpSetHiInt32x8
	OpSetHiInt32x16
	OpSetHiInt64x4
	OpSetHiInt64x8
	OpSetHiUint8x32
	OpSetHiUint8x64
	OpSetHiUint16x16
	OpSetHiUint16x32
	OpSetHiUint32x8
	OpSetHiUint32x16
	OpSetHiUint64x4
	OpSetHiUint64x8
	OpSetLoFloat32x8
	OpSetLoFloat32x16
	OpSetLoFloat64x4
	OpSetLoFloat64x8
	OpSetLoInt8x32
	OpSetLoInt8x64
	OpSetLoInt16x16
	OpSetLoInt16x32
	OpSetLoInt32x8
	OpSetLoInt32x16
	OpSetLoInt64x4
	OpSetLoInt64x8
	OpSetLoUint8x32
	OpSetLoUint8x64
	OpSetLoUint16x16
	OpSetLoUint16x32
	OpSetLoUint32x8
	OpSetLoUint32x16
	OpSetLoUint64x4
	OpSetLoUint64x8
	OpShiftAllLeftInt8x16
	OpShiftAllLeftInt16x8
	OpShiftAllLeftInt16x16
	OpShiftAllLeftInt16x32
	OpShiftAllLeftInt32x4
	OpShiftAllLeftInt32x8
	OpShiftAllLeftInt32x16
	OpShiftAllLeftInt64x2
	OpShiftAllLeftInt64x4
	OpShiftAllLeftInt64x8
	OpShiftAllLeftUint8x16
	OpShiftAllLeftUint16x8
	OpShiftAllLeftUint16x16
	OpShiftAllLeftUint16x32
	OpShiftAllLeftUint32x4
	OpShiftAllLeftUint32x8
	OpShiftAllLeftUint32x16
	OpShiftAllLeftUint64x2
	OpShiftAllLeftUint64x4
	OpShiftAllLeftUint64x8
	OpShiftAllRightInt8x16
	OpShiftAllRightInt16x8
	OpShiftAllRightInt16x16
	OpShiftAllRightInt16x32
	OpShiftAllRightInt32x4
	OpShiftAllRightInt32x8
	OpShiftAllRightInt32x16
	OpShiftAllRightInt64x2
	OpShiftAllRightInt64x4
	OpShiftAllRightInt64x8
	OpShiftAllRightUint8x16
	OpShiftAllRightUint16x8
	OpShiftAllRightUint16x16
	OpShiftAllRightUint16x32
	OpShiftAllRightUint32x4
	OpShiftAllRightUint32x8
	OpShiftAllRightUint32x16
	OpShiftAllRightUint64x2
	OpShiftAllRightUint64x4
	OpShiftAllRightUint64x8
	OpShiftInt8x16
	OpShiftInt16x8
	OpShiftInt32x4
	OpShiftInt64x2
	OpShiftLeftConcatMod16Int16x8
	OpShiftLeftConcatMod16Int16x16
	OpShiftLeftConcatMod16Int16x32
	OpShiftLeftConcatMod16Uint16x8
	OpShiftLeftConcatMod16Uint16x16
	OpShiftLeftConcatMod16Uint16x32
	OpShiftLeftConcatMod32Int32x4
	OpShiftLeftConcatMod32Int32x8
	OpShiftLeftConcatMod32Int32x16
	OpShiftLeftConcatMod32Uint32x4
	OpShiftLeftConcatMod32Uint32x8
	OpShiftLeftConcatMod32Uint32x16
	OpShiftLeftConcatMod64Int64x2
	OpShiftLeftConcatMod64Int64x4
	OpShiftLeftConcatMod64Int64x8
	OpShiftLeftConcatMod64Uint64x2
	OpShiftLeftConcatMod64Uint64x4
	OpShiftLeftConcatMod64Uint64x8
	OpShiftLeftInt16x8
	OpShiftLeftInt16x16
	OpShiftLeftInt16x32
	OpShiftLeftInt32x4
	OpShiftLeftInt32x8
	OpShiftLeftInt32x16
	OpShiftLeftInt64x2
	OpShiftLeftInt64x4
	OpShiftLeftInt64x8
	OpShiftLeftUint16x8
	OpShiftLeftUint16x16
	OpShiftLeftUint16x32
	OpShiftLeftUint32x4
	OpShiftLeftUint32x8
	OpShiftLeftUint32x16
	OpShiftLeftUint64x2
	OpShiftLeftUint64x4
	OpShiftLeftUint64x8
	OpShiftRightConcatMod16Int16x8
	OpShiftRightConcatMod16Int16x16
	OpShiftRightConcatMod16Int16x32
	OpShiftRightConcatMod16Uint16x8
	OpShiftRightConcatMod16Uint16x16
	OpShiftRightConcatMod16Uint16x32
	OpShiftRightConcatMod32Int32x4
	OpShiftRightConcatMod32Int32x8
	OpShiftRightConcatMod32Int32x16
	OpShiftRightConcatMod32Uint32x4
	OpShiftRightConcatMod32Uint32x8
	OpShiftRightConcatMod32Uint32x16
	OpShiftRightConcatMod64Int64x2
	OpShiftRightConcatMod64Int64x4
	OpShiftRightConcatMod64Int64x8
	OpShiftRightConcatMod64Uint64x2
	OpShiftRightConcatMod64Uint64x4
	OpShiftRightConcatMod64Uint64x8
	OpShiftRightInt16x8
	OpShiftRightInt16x16
	OpShiftRightInt16x32
	OpShiftRightInt32x4
	OpShiftRightInt32x8
	OpShiftRightInt32x16
	OpShiftRightInt64x2
	OpShiftRightInt64x4
	OpShiftRightInt64x8
	OpShiftRightUint16x8
	OpShiftRightUint16x16
	OpShiftRightUint16x32
	OpShiftRightUint32x4
	OpShiftRightUint32x8
	OpShiftRightUint32x16
	OpShiftRightUint64x2
	OpShiftRightUint64x4
	OpShiftRightUint64x8
	OpShiftSaturatedInt8x16
	OpShiftSaturatedInt16x8
	OpShiftSaturatedInt32x4
	OpShiftSaturatedInt64x2
	OpShiftSaturatedUint8x16
	OpShiftSaturatedUint16x8
	OpShiftSaturatedUint32x4
	OpShiftSaturatedUint64x2
	OpShiftUint8x16
	OpShiftUint16x8
	OpShiftUint32x4
	OpShiftUint64x2
	OpSqrtFloat32x4
	OpSqrtFloat32x8
	OpSqrtFloat32x16
	OpSqrtFloat64x2
	OpSqrtFloat64x4
	OpSqrtFloat64x8
	OpSubFloat32x4
	OpSubFloat32x8
	OpSubFloat32x16
	OpSubFloat64x2
	OpSubFloat64x4
	OpSubFloat64x8
	OpSubInt8x16
	OpSubInt8x32
	OpSubInt8x64
	OpSubInt16x8
	OpSubInt16x16
	OpSubInt16x32
	OpSubInt32x4
	OpSubInt32x8
	OpSubInt32x16
	OpSubInt64x2
	OpSubInt64x4
	OpSubInt64x8
	OpSubSaturatedInt8x16
	OpSubSaturatedInt8x32
	OpSubSaturatedInt8x64
	OpSubSaturatedInt16x8
	OpSubSaturatedInt16x16
	OpSubSaturatedInt16x32
	OpSubSaturatedInt32x4
	OpSubSaturatedInt64x2
	OpSubSaturatedUint8x16
	OpSubSaturatedUint8x32
	OpSubSaturatedUint8x64
	OpSubSaturatedUint16x8
	OpSubSaturatedUint16x16
	OpSubSaturatedUint16x32
	OpSubSaturatedUint32x4
	OpSubSaturatedUint64x2
	OpSubUint8x16
	OpSubUint8x32
	OpSubUint8x64
	OpSubUint16x8
	OpSubUint16x16
	OpSubUint16x32
	OpSubUint32x4
	OpSubUint32x8
	OpSubUint32x16
	OpSubUint64x2
	OpSubUint64x4
	OpSubUint64x8
	OpSumOf8AbsDiffUint8x16
	OpSumOf8AbsDiffUint8x32
	OpSumOf8AbsDiffUint8x64
	OpTruncFloat32x4
	OpTruncFloat32x8
	OpTruncFloat64x2
	OpTruncFloat64x4
	OpTruncToInt8Int16x8
	OpTruncToInt8Int16x16
	OpTruncToInt8Int16x32
	OpTruncToInt8Int32x4
	OpTruncToInt8Int32x8
	OpTruncToInt8Int32x16
	OpTruncToInt8Int64x2
	OpTruncToInt8Int64x4
	OpTruncToInt8Int64x8
	OpTruncToInt16Int32x4
	OpTruncToInt16Int32x8
	OpTruncToInt16Int32x16
	OpTruncToInt16Int64x2
	OpTruncToInt16Int64x4
	OpTruncToInt16Int64x8
	OpTruncToInt32Int64x2
	OpTruncToInt32Int64x4
	OpTruncToInt32Int64x8
	OpTruncToUint8Uint16x8
	OpTruncToUint8Uint16x16
	OpTruncToUint8Uint16x32
	OpTruncToUint8Uint32x4
	OpTruncToUint8Uint32x8
	OpTruncToUint8Uint32x16
	OpTruncToUint8Uint64x2
	OpTruncToUint8Uint64x4
	OpTruncToUint8Uint64x8
	OpTruncToUint16Uint32x4
	OpTruncToUint16Uint32x8
	OpTruncToUint16Uint32x16
	OpTruncToUint16Uint64x2
	OpTruncToUint16Uint64x4
	OpTruncToUint16Uint64x8
	OpTruncToUint32Uint64x2
	OpTruncToUint32Uint64x4
	OpTruncToUint32Uint64x8
	OpXorInt8x16
	OpXorInt8x32
	OpXorInt8x64
	OpXorInt16x8
	OpXorInt16x16
	OpXorInt16x32
	OpXorInt32x4
	OpXorInt32x8
	OpXorInt32x16
	OpXorInt64x2
	OpXorInt64x4
	OpXorInt64x8
	OpXorUint8x16
	OpXorUint8x32
	OpXorUint8x64
	OpXorUint16x8
	OpXorUint16x16
	OpXorUint16x32
	OpXorUint32x4
	OpXorUint32x8
	OpXorUint32x16
	OpXorUint64x2
	OpXorUint64x4
	OpXorUint64x8
	OpbitSelectInt8x16
	OpbitSelectNotInt8x16
	OpblendInt8x16
	OpblendInt8x32
	OpblendMaskedInt8x64
	OpblendMaskedInt16x32
	OpblendMaskedInt32x16
	OpblendMaskedInt64x8
	Opbroadcast1To2Float64x2
	Opbroadcast1To2Int64x2
	Opbroadcast1To2MaskedFloat64x2
	Opbroadcast1To2MaskedInt64x2
	Opbroadcast1To2MaskedUint64x2
	Opbroadcast1To2Uint64x2
	Opbroadcast1To4Float32x4
	Opbroadcast1To4Float64x2
	Opbroadcast1To4Int32x4
	Opbroadcast1To4Int64x2
	Opbroadcast1To4MaskedFloat32x4
	Opbroadcast1To4MaskedFloat64x2
	Opbroadcast1To4MaskedInt32x4
	Opbroadcast1To4MaskedInt64x2
	Opbroadcast1To4MaskedUint32x4
	Opbroadcast1To4MaskedUint64x2
	Opbroadcast1To4Uint32x4
	Opbroadcast1To4Uint64x2
	Opbroadcast1To8Float32x4
	Opbroadcast1To8Float64x2
	Opbroadcast1To8Int16x8
	Opbroadcast1To8Int32x4
	Opbroadcast1To8Int64x2
	Opbroadcast1To8MaskedFloat32x4
	Opbroadcast1To8MaskedFloat64x2
	Opbroadcast1To8MaskedInt16x8
	Opbroadcast1To8MaskedInt32x4
	Opbroadcast1To8MaskedInt64x2
	Opbroadcast1To8MaskedUint16x8
	Opbroadcast1To8MaskedUint32x4
	Opbroadcast1To8MaskedUint64x2
	Opbroadcast1To8Uint16x8
	Opbroadcast1To8Uint32x4
	Opbroadcast1To8Uint64x2
	Opbroadcast1To16Float32x4
	Opbroadcast1To16Int8x16
	Opbroadcast1To16Int16x8
	Opbroadcast1To16Int32x4
	Opbroadcast1To16MaskedFloat32x4
	Opbroadcast1To16MaskedInt8x16
	Opbroadcast1To16MaskedInt16x8
	Opbroadcast1To16MaskedInt32x4
	Opbroadcast1To16MaskedUint8x16
	Opbroadcast1To16MaskedUint16x8
	Opbroadcast1To16MaskedUint32x4
	Opbroadcast1To16Uint8x16
	Opbroadcast1To16Uint16x8
	Opbroadcast1To16Uint32x4
	Opbroadcast1To32Int8x16
	Opbroadcast1To32Int16x8
	Opbroadcast1To32MaskedInt8x16
	Opbroadcast1To32MaskedInt16x8
	Opbroadcast1To32MaskedUint8x16
	Opbroadcast1To32MaskedUint16x8
	Opbroadcast1To32Uint8x16
	Opbroadcast1To32Uint16x8
	Opbroadcast1To64Int8x16
	Opbroadcast1To64MaskedInt8x16
	Opbroadcast1To64MaskedUint8x16
	Opbroadcast1To64Uint8x16
	OpcarrylessMultiplyWidenLoUint64x2
	OpreduceMaxFloat32x4
	OpreduceMaxInt8x16
	OpreduceMaxInt16x8
	OpreduceMaxInt32x4
	OpreduceMaxUint8x16
	OpreduceMaxUint16x8
	OpreduceMaxUint32x4
	OpreduceMinFloat32x4
	OpreduceMinInt8x16
	OpreduceMinInt16x8
	OpreduceMinInt32x4
	OpreduceMinUint8x16
	OpreduceMinUint16x8
	OpreduceMinUint32x4
	OpreduceSumInt8x16
	OpreduceSumInt16x8
	OpreduceSumInt32x4
	OpreduceSumUint8x16
	OpreduceSumUint16x8
	OpreduceSumUint32x4
	OpAESRoundKeyGenAssistUint32x4
	OpCeilScaledFloat32x4
	OpCeilScaledFloat32x8
	OpCeilScaledFloat32x16
	OpCeilScaledFloat64x2
	OpCeilScaledFloat64x4
	OpCeilScaledFloat64x8
	OpCeilScaledResidueFloat32x4
	OpCeilScaledResidueFloat32x8
	OpCeilScaledResidueFloat32x16
	OpCeilScaledResidueFloat64x2
	OpCeilScaledResidueFloat64x4
	OpCeilScaledResidueFloat64x8
	OpConcatPermute128ScalarsFloat32x8
	OpConcatPermute128ScalarsFloat64x4
	OpConcatPermute128ScalarsInt8x32
	OpConcatPermute128ScalarsInt16x16
	OpConcatPermute128ScalarsInt32x8
	OpConcatPermute128ScalarsInt64x4
	OpConcatPermute128ScalarsUint8x32
	OpConcatPermute128ScalarsUint16x16
	OpConcatPermute128ScalarsUint32x8
	OpConcatPermute128ScalarsUint64x4
	OpConcatShiftBytesRightGroupedUint8x32
	OpConcatShiftBytesRightGroupedUint8x64
	OpConcatShiftBytesRightUint8x16
	OpFloorScaledFloat32x4
	OpFloorScaledFloat32x8
	OpFloorScaledFloat32x16
	OpFloorScaledFloat64x2
	OpFloorScaledFloat64x4
	OpFloorScaledFloat64x8
	OpFloorScaledResidueFloat32x4
	OpFloorScaledResidueFloat32x8
	OpFloorScaledResidueFloat32x16
	OpFloorScaledResidueFloat64x2
	OpFloorScaledResidueFloat64x4
	OpFloorScaledResidueFloat64x8
	OpGaloisFieldAffineTransformInverseUint8x16
	OpGaloisFieldAffineTransformInverseUint8x32
	OpGaloisFieldAffineTransformInverseUint8x64
	OpGaloisFieldAffineTransformUint8x16
	OpGaloisFieldAffineTransformUint8x32
	OpGaloisFieldAffineTransformUint8x64
	OpGetElemFloat32x4
	OpGetElemFloat64x2
	OpGetElemInt8x16
	OpGetElemInt16x8
	OpGetElemInt32x4
	OpGetElemInt64x2
	OpGetElemUint8x16
	OpGetElemUint16x8
	OpGetElemUint32x4
	OpGetElemUint64x2
	OpRoundScaledFloat32x4
	OpRoundScaledFloat32x8
	OpRoundScaledFloat32x16
	OpRoundScaledFloat64x2
	OpRoundScaledFloat64x4
	OpRoundScaledFloat64x8
	OpRoundScaledResidueFloat32x4
	OpRoundScaledResidueFloat32x8
	OpRoundScaledResidueFloat32x16
	OpRoundScaledResidueFloat64x2
	OpRoundScaledResidueFloat64x4
	OpRoundScaledResidueFloat64x8
	OpSHA1FourRoundsUint32x4
	OpSetElemFloat32x4
	OpSetElemFloat64x2
	OpSetElemInt8x16
	OpSetElemInt16x8
	OpSetElemInt32x4
	OpSetElemInt64x2
	OpSetElemUint8x16
	OpSetElemUint16x8
	OpSetElemUint32x4
	OpSetElemUint64x2
	OpShiftAllLeftConcatMod16Int16x8
	OpShiftAllLeftConcatMod16Int16x16
	OpShiftAllLeftConcatMod16Int16x32
	OpShiftAllLeftConcatMod16Uint16x8
	OpShiftAllLeftConcatMod16Uint16x16
	OpShiftAllLeftConcatMod16Uint16x32
	OpShiftAllLeftConcatMod32Int32x4
	OpShiftAllLeftConcatMod32Int32x8
	OpShiftAllLeftConcatMod32Int32x16
	OpShiftAllLeftConcatMod32Uint32x4
	OpShiftAllLeftConcatMod32Uint32x8
	OpShiftAllLeftConcatMod32Uint32x16
	OpShiftAllLeftConcatMod64Int64x2
	OpShiftAllLeftConcatMod64Int64x4
	OpShiftAllLeftConcatMod64Int64x8
	OpShiftAllLeftConcatMod64Uint64x2
	OpShiftAllLeftConcatMod64Uint64x4
	OpShiftAllLeftConcatMod64Uint64x8
	OpShiftAllRightConcatMod16Int16x8
	OpShiftAllRightConcatMod16Int16x16
	OpShiftAllRightConcatMod16Int16x32
	OpShiftAllRightConcatMod16Uint16x8
	OpShiftAllRightConcatMod16Uint16x16
	OpShiftAllRightConcatMod16Uint16x32
	OpShiftAllRightConcatMod32Int32x4
	OpShiftAllRightConcatMod32Int32x8
	OpShiftAllRightConcatMod32Int32x16
	OpShiftAllRightConcatMod32Uint32x4
	OpShiftAllRightConcatMod32Uint32x8
	OpShiftAllRightConcatMod32Uint32x16
	OpShiftAllRightConcatMod64Int64x2
	OpShiftAllRightConcatMod64Int64x4
	OpShiftAllRightConcatMod64Int64x8
	OpShiftAllRightConcatMod64Uint64x2
	OpShiftAllRightConcatMod64Uint64x4
	OpShiftAllRightConcatMod64Uint64x8
	OpTruncScaledFloat32x4
	OpTruncScaledFloat32x8
	OpTruncScaledFloat32x16
	OpTruncScaledFloat64x2
	OpTruncScaledFloat64x4
	OpTruncScaledFloat64x8
	OpTruncScaledResidueFloat32x4
	OpTruncScaledResidueFloat32x8
	OpTruncScaledResidueFloat32x16
	OpTruncScaledResidueFloat64x2
	OpTruncScaledResidueFloat64x4
	OpTruncScaledResidueFloat64x8
	OpcarrylessMultiplyUint64x2
	OpcarrylessMultiplyUint64x4
	OpcarrylessMultiplyUint64x8
	OpconcatSelectedConstantFloat32x4
	OpconcatSelectedConstantFloat64x2
	OpconcatSelectedConstantGroupedFloat32x8
	OpconcatSelectedConstantGroupedFloat32x16
	OpconcatSelectedConstantGroupedFloat64x4
	OpconcatSelectedConstantGroupedFloat64x8
	OpconcatSelectedConstantGroupedInt32x8
	OpconcatSelectedConstantGroupedInt32x16
	OpconcatSelectedConstantGroupedInt64x4
	OpconcatSelectedConstantGroupedInt64x8
	OpconcatSelectedConstantGroupedUint32x8
	OpconcatSelectedConstantGroupedUint32x16
	OpconcatSelectedConstantGroupedUint64x4
	OpconcatSelectedConstantGroupedUint64x8
	OpconcatSelectedConstantInt32x4
	OpconcatSelectedConstantInt64x2
	OpconcatSelectedConstantUint32x4
	OpconcatSelectedConstantUint64x2
	OppermuteScalarsGroupedInt32x8
	OppermuteScalarsGroupedInt32x16
	OppermuteScalarsGroupedUint32x8
	OppermuteScalarsGroupedUint32x16
	OppermuteScalarsHiGroupedInt16x16
	OppermuteScalarsHiGroupedInt16x32
	OppermuteScalarsHiGroupedUint16x16
	OppermuteScalarsHiGroupedUint16x32
	OppermuteScalarsHiInt16x8
	OppermuteScalarsHiUint16x8
	OppermuteScalarsInt32x4
	OppermuteScalarsLoGroupedInt16x16
	OppermuteScalarsLoGroupedInt16x32
	OppermuteScalarsLoGroupedUint16x16
	OppermuteScalarsLoGroupedUint16x32
	OppermuteScalarsLoInt16x8
	OppermuteScalarsLoUint16x8
	OppermuteScalarsUint32x4
	OpternInt32x4
	OpternInt32x8
	OpternInt32x16
	OpternInt64x2
	OpternInt64x4
	OpternInt64x8
	OpternUint32x4
	OpternUint32x8
	OpternUint32x16
	OpternUint64x2
	OpternUint64x4
	OpternUint64x8
)

var opcodeTable = [...]opInfo{
	{name: "OpInvalid"},

	{
		name:         "ADDSS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AADDSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "ADDSD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AADDSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "SUBSS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ASUBSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "SUBSD",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ASUBSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MULSS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMULSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MULSD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMULSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "DIVSS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ADIVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "DIVSD",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ADIVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "MOVSSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "MOVSDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:              "MOVSSconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVSS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:              "MOVSDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVSD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MOVSSloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MOVSSloadidx4",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MOVSDloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "MOVSDloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "MOVSSstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVSDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVSSstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVSSstoreidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVSDstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVSDstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ADDSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "ADDSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "SUBSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "SUBSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "MULSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AMULSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "MULSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AMULSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "DIVSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ADIVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:           "DIVSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ADIVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "ADDL",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADDLconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADDLcarry",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADDLconstcarry",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADCL",
		argLen:       3,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.AADCL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADCLcarry",
		argLen:       3,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.AADCL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADCLconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.AADCL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SUBL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SUBLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SUBLcarry",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SUBLconstcarry",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SBBL",
		argLen:       3,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.ASBBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SBBLconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          x86.ASBBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MULL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MULLconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMUL3L,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MULLU",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "HMULL",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "HMULLU",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "MULLQU",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
				{1, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "AVGLU",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "DIVL",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "DIVW",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "DIVLU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "DIVWU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "MODL",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "MODW",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "MODLU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "MODWU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},   // AX
				{1, regMask{v1: 251, v2: 0}}, // AX CX BX SP BP SI DI
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "ANDL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ANDLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ORL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ORLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "XORL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "XORLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:   "CMPL",
		argLen: 2,
		asm:    x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:   "CMPB",
		argLen: 2,
		asm:    x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "CMPLconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "CMPWconst",
		auxType: auxInt16,
		argLen:  1,
		asm:     x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "CMPBconst",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:           "CMPLload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "CMPWload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "CMPBload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "CMPLconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "CMPWconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "CMPBconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:    "UCOMISS",
		argLen:  2,
		earlyOk: true,
		asm:     x86.AUCOMISS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "UCOMISD",
		argLen:  2,
		earlyOk: true,
		asm:     x86.AUCOMISD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:        "TESTL",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:        "TESTW",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:        "TESTB",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "TESTLconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ATESTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "TESTWconst",
		auxType: auxInt16,
		argLen:  1,
		asm:     x86.ATESTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:    "TESTBconst",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.ATESTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:         "SHLL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHLLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRWconst",
		auxType:      auxInt16,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SHRBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARWconst",
		auxType:      auxInt16,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SARBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},   // CX
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLWconst",
		auxType:      auxInt16,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ROLBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "ADDLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "SUBLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MULLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "ANDLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "ORLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "XORLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ADDLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SUBLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MULLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ANDLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "ORLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "XORLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}},   // AX CX DX BX BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{1, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "NEGL",
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ANEGL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "NOTL",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ANOTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "BSFL",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSFL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "BSFW",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "LoweredCtz32",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:            "LoweredCtz64",
		argLen:          2,
		resultNotInArgs: true,
		clobberFlags:    true,
		earlyOk:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "BSRL",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "BSRW",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "BSWAPL",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ABSWAPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SQRTSD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASQRTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "SQRTSS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASQRTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "SBBLcarrymask",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASBBL,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETEQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETEQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETNE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETNE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLT,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETLE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETG",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETGT,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETGE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETGE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETB",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETBE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETA",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETHI,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETAE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETO",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETOS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SETEQF",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASETEQ,
		reg: regInfo{
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 238, v2: 0}}, // CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "SETNEF",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASETNE,
		reg: regInfo{
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 238, v2: 0}}, // CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETORD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETPC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETNAN",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETPS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETGF",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETHI,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "SETGEF",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVBLSX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVBLSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVBLZX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVBLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVWLSX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVWLSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVWLZX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:              "MOVLconst",
		auxType:           auxInt32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVL,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "CVTTSD2SL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSD2SL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "CVTTSS2SL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSS2SL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "CVTSL2SS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSL2SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "CVTSL2SD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSL2SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "CVTSD2SS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSD2SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "CVTSS2SD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSS2SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:         "PXOR",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.APXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
				{1, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:              "LEAL",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:        "LEAL1",
		auxType:     auxSymOff,
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		symEffect:   SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:      "LEAL2",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:      "LEAL4",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:      "LEAL8",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVBLSXload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBLSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVWLSXload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVWLSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVLload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVLstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ADDLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "SUBLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ANDLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ORLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "XORLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ADDLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "SUBLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ANDLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ORLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "XORLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ADDLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ANDLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "ORLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "XORLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ADDLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ANDLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "ORLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "XORLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVBloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MOVWloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MOVWloadidx2",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MOVLloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MOVLloadidx4",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:         "MOVBstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVWstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVWstoreidx2",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVLstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVLstoreidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{2, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVBstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVWstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "MOVLstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVBstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVWstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVWstoreconstidx2",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVLstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:         "MOVLstoreconstidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 255, v2: 0}},   // AX CX DX BX SP BP SI DI
				{0, regMask{v1: 65791, v2: 0}}, // AX CX DX BX SP BP SI DI SB
			},
		},
	},
	{
		name:           "DUFFZERO",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 1, v2: 0}},   // AX
			},
			clobbers: regMask{v1: 130, v2: 0}, // CX DI
		},
	},
	{
		name:           "REPSTOSL",
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 2, v2: 0}},   // CX
				{2, regMask{v1: 1, v2: 0}},   // AX
			},
			clobbers: regMask{v1: 130, v2: 0}, // CX DI
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       3,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4, v2: 0}},   // DX
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
			clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			clobbers: regMask{v1: 65519, v2: 0}, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
		},
	},
	{
		name:           "DUFFCOPY",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 64, v2: 0}},  // SI
			},
			clobbers: regMask{v1: 194, v2: 0}, // CX SI DI
		},
	},
	{
		name:           "REPMOVSL",
		argLen:         4,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 64, v2: 0}},  // SI
				{2, regMask{v1: 2, v2: 0}},   // CX
			},
			clobbers: regMask{v1: 194, v2: 0}, // CX SI DI
		},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:   "LoweredGetG",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		clobberFlags:   true,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 255, v2: 0}}, // AX CX DX BX SP BP SI DI
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 65280, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7
			outputs: []outputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
				{1, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:    "LoweredPanicExtendRR",
		auxType: auxInt64,
		argLen:  4,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 15, v2: 0}},  // AX CX DX BX
				{1, regMask{v1: 15, v2: 0}},  // AX CX DX BX
				{2, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "LoweredPanicExtendRC",
		auxType: auxPanicBoundsC,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 15, v2: 0}}, // AX CX DX BX
				{1, regMask{v1: 15, v2: 0}}, // AX CX DX BX
			},
		},
	},
	{
		name:   "FlagEQ",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT_ULT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT_UGT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT_UGT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT_ULT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:    "MOVSSconst1",
		auxType: auxFloat32,
		argLen:  0,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVSDconst1",
		auxType: auxFloat64,
		argLen:  0,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
		},
	},
	{
		name:    "MOVSSconst2",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},
	{
		name:    "MOVSDconst2",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 239, v2: 0}}, // AX CX DX BX BP SI DI
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65280, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7
			},
		},
	},

	{
		name:         "ADDSS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AADDSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDSD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AADDSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ASUBSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSD",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ASUBSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMULSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMULSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ADIVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSD",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ADIVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MOVSSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MOVSDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:              "MOVSSconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVSS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:              "MOVSDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVSD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MOVSSloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MOVSSloadidx4",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MOVSDloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MOVSDloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MOVSSstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:           "MOVSDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:         "MOVSSstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:         "MOVSSstoreidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:         "MOVSDstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:         "MOVSDstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:           "ADDSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "ADDSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "SUBSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "SUBSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MULSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AMULSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MULSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AMULSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "DIVSSload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ADIVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "DIVSDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ADIVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDSSloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDSSloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDSDloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDSDloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSSloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSSloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSDloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SUBSDloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSSloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMULSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSSloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMULSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSDloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMULSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MULSDloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMULSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSSloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ADIVSS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSSloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ADIVSS,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSDloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ADIVSD,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "DIVSDloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ADIVSD,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "ADDQ",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDL",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDLconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ADDQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ADDLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBQconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULQ",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULQconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMUL3Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULLconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMUL3L,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULLU",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		asm:          x86.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "MULQU",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		asm:          x86.AMULQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 4, v2: 0}, // DX
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "HMULQ",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "HMULL",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AIMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "HMULQU",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "HMULLU",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "AVGQU",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "DIVQ",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "DIVL",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "DIVW",
		auxType:      auxBool,
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AIDIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "DIVQU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "DIVLU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "DIVWU",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49147, v2: 0}}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "NEGLflags",
		argLen:       1,
		resultInArg0: true,
		asm:          x86.ANEGL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQconstflags",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDLconstflags",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQcarry",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		asm:          x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADCQ",
		argLen:       3,
		commutative:  true,
		resultInArg0: true,
		asm:          x86.AADCQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQconstcarry",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADCQconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		asm:          x86.AADCQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBQborrow",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SBBQ",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.ASBBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBQconstborrow",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		asm:          x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SBBQconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASBBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MULQU2",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AMULQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}},     // AX
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
				{1, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:         "DIVQU2",
		argLen:       3,
		clobberFlags: true,
		asm:          x86.ADIVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}},     // DX
				{1, regMask{v1: 1, v2: 0}},     // AX
				{2, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // AX
				{1, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:         "ANDQ",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDQconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ANDQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ANDLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORQ",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORQconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ORQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORQ",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORQconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORLconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XORQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "XORLconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:   "CMPQ",
		argLen: 2,
		asm:    x86.ACMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "CMPL",
		argLen: 2,
		asm:    x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "CMPB",
		argLen: 2,
		asm:    x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CMPQconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ACMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CMPLconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CMPWconst",
		auxType: auxInt16,
		argLen:  1,
		asm:     x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CMPBconst",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "CMPQload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPLload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPWload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPBload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPQconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPLconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPWconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "CMPBconstload",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ACMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPWloadidx2",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPW,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPWloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPW,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPBloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPB,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPQconstloadidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPQconstloadidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPLconstloadidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPLconstloadidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPWconstloadidx2",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.ACMPW,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPWconstloadidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPW,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "CMPBconstloadidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ACMPB,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:   "UCOMISS",
		argLen: 2,
		asm:    x86.AUCOMISS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "UCOMISD",
		argLen: 2,
		asm:    x86.AUCOMISD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "BTL",
		argLen: 2,
		asm:    x86.ABTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "BTQ",
		argLen: 2,
		asm:    x86.ABTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTCL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTCL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTCQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTCQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTRL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTRQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTSL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTSL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTSQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "BTLconst",
		auxType: auxInt8,
		argLen:  1,
		earlyOk: true,
		asm:     x86.ABTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "BTQconst",
		auxType: auxInt8,
		argLen:  1,
		earlyOk: true,
		asm:     x86.ABTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTCQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTCQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTRQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BTSQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABTSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "BTSQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ABTSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "BTRQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ABTRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "BTCQconstmodify",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ABTCQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:        "TESTQ",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "TESTL",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "TESTW",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "TESTB",
		argLen:      2,
		commutative: true,
		asm:         x86.ATESTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "TESTQconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ATESTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "TESTLconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     x86.ATESTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "TESTWconst",
		auxType: auxInt16,
		argLen:  1,
		asm:     x86.ATESTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "TESTBconst",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.ATESTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHLQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHLL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHLQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHLLconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRLconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRWconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SHRBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASHRB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARLconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARWconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SARBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ASARB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "RORQ",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ARORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "RORL",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ARORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "RORW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ARORW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "RORB",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ARORB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // CX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLQconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLLconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLWconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ROLBconst",
		auxType:      auxInt8,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.AROLB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ADDLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ADDQload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SUBQload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SUBLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ANDLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ANDQload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ORQload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ORLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XORQload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XORLload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDLloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ADDQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AADDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBLloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SUBQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.ASUBQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDLloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AANDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORLloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ORQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORLloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORLloadidx4",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORLloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORQloadidx1",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "XORQloadidx8",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		clobberFlags: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AXORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ADDQmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SUBQmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ASUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ANDQmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORQmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "XORQmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ADDLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SUBLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.ASUBL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ANDLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "XORLmodify",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead | SymWrite,
		asm:            x86.AXORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDQmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDQmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBQmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBQmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDQmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDQmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORQmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORQmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORQmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORQmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBLmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SUBLmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.ASUBL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLmodifyidx1",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLmodifyidx4",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLmodifyidx8",
		auxType:      auxSymOff,
		argLen:       4,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDQconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDQconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDQconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDQconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORQconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORQconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORQconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORQconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ADDLconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AADDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDLconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AANDL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ORLconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLconstmodifyidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLconstmodifyidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "XORLconstmodifyidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		clobberFlags: true,
		addrSinkArg0: true,
		symEffect:    SymRead | SymWrite,
		asm:          x86.AXORL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "NEGQ",
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ANEGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "NEGL",
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ANEGL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "NOTQ",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ANOTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "NOTL",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ANOTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "BSFQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ABSFQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BSFL",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSFL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "BSRQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ABSRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BSRL",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          x86.ABSRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQEQ",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQNE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQLT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQLT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQGT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQLE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQLE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQGE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQLS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQHI",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQCC",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQCS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLEQ",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLNE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLLT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLLT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLGT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLLE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLLE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLGE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLLS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLHI",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLCC",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLCS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWEQ",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWNE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWLT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWLT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWGT",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWLE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWLE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWGE",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWLS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWHI",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWCC",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWCS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQEQF",
		argLen:       3,
		resultInArg0: true,
		needIntTemp:  true,
		earlyOk:      true,
		asm:          x86.ACMOVQNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQNEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQGTF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVQGEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVQCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLEQF",
		argLen:       3,
		resultInArg0: true,
		needIntTemp:  true,
		earlyOk:      true,
		asm:          x86.ACMOVLNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLNEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLGTF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVLGEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVLCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWEQF",
		argLen:       3,
		resultInArg0: true,
		needIntTemp:  true,
		earlyOk:      true,
		asm:          x86.ACMOVWNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWNEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWGTF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "CMOVWGEF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ACMOVWCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BSWAPQ",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ABSWAPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BSWAPL",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.ABSWAPL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "POPCNTQ",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.APOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "POPCNTL",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.APOPCNTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SQRTSD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASQRTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "SQRTSS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASQRTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "ROUNDSD",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.AROUNDSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "ROUNDSS",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.AROUNDSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD231SS",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD231SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD231SD",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD231SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{2, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MINSD",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "MINSS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.AMINSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "SBBQcarrymask",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASBBQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SBBLcarrymask",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASBBL,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETEQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETEQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETNE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETNE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLT,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETLE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETG",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETGT,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETGE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETGE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETB",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETBE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETLS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETA",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETHI,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETAE",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETO",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETOS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SETEQstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETNEstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETNE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETLstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETLT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETLEstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETLE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETGstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETGEstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETBEstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETAstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "SETAEstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.ASETCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETEQstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETEQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETNEstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETNE,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETLstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETLT,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETLEstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETLE,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETGstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETGT,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETGEstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETGE,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETBstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETCS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETBEstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETLS,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETAstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETHI,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETAEstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.ASETCC,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "SETEQF",
		argLen:       1,
		clobberFlags: true,
		needIntTemp:  true,
		earlyOk:      true,
		asm:          x86.ASETEQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "SETNEF",
		argLen:       1,
		clobberFlags: true,
		needIntTemp:  true,
		earlyOk:      true,
		asm:          x86.ASETNE,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETORD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETPC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETNAN",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETPS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETGF",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETHI,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "SETGEF",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ASETCC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVBQSX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVBQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVBQZX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVBLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVWQSX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVWQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVWQZX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVLQSX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVLQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVLQZX",
		argLen:  1,
		earlyOk: true,
		asm:     x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:              "MOVLconst",
		auxType:           auxInt32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVL,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:              "MOVQconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               x86.AMOVQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CVTTSD2SL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSD2SL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CVTTSD2SQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSD2SQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CVTTSS2SL",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSS2SL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CVTTSS2SQ",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTTSS2SQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "CVTSL2SS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSL2SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "CVTSL2SD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSL2SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "CVTSQ2SS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSQ2SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "CVTSQ2SD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSQ2SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "CVTSD2SS",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSD2SS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "CVTSS2SD",
		argLen:  1,
		earlyOk: true,
		asm:     x86.ACVTSS2SD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "MOVQi2f",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "MOVQf2i",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "MOVLi2f",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "MOVLf2i",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "PXOR",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.APXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "POR",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          x86.APOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:              "LEAQ",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               x86.ALEAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:              "LEAL",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               x86.ALEAL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:              "LEAW",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               x86.ALEAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "LEAQ1",
		auxType:     auxSymOff,
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		symEffect:   SymAddr,
		asm:         x86.ALEAQ,
		scale:       1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "LEAL1",
		auxType:     auxSymOff,
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		symEffect:   SymAddr,
		asm:         x86.ALEAL,
		scale:       1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:        "LEAW1",
		auxType:     auxSymOff,
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		symEffect:   SymAddr,
		asm:         x86.ALEAW,
		scale:       1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAQ2",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAQ,
		scale:     2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAL2",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAL,
		scale:     2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAW2",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAW,
		scale:     2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAQ4",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAQ,
		scale:     4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAL4",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAL,
		scale:     4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAW4",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAW,
		scale:     4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAQ8",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAQ,
		scale:     8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAL8",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAL,
		scale:     8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LEAW8",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		asm:       x86.ALEAW,
		scale:     8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBQSXload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVWLZX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVWQSXload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVWQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVLload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVLQSXload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVLQSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVQload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVLstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVQstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVOload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVUPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "MOVOstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVUPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:         "MOVBloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBLZX,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVWloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVWLZX,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVWloadidx2",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVWLZX,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVLloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVLloadidx4",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVLloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVQloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVQloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVB,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVWstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVWstoreidx2",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVLstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVLstoreidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVLstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVQstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVQstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVBstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVWstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVLstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVQstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVOstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVUPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVB,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVWstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVWstoreconstidx2",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVW,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVLstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVLstoreconstidx4",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVQstoreconstidx1",
		auxType:      auxSymValAndOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVQstoreconstidx8",
		auxType:      auxSymValAndOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "LoweredZeroLoop",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		needIntTemp:    true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbersArg0: true,
		},
	},
	{
		name:           "REPSTOSQ",
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 2, v2: 0}},   // CX
				{2, regMask{v1: 1, v2: 0}},   // AX
			},
			clobbers: regMask{v1: 130, v2: 0}, // CX DI
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4, v2: 0}},     // DX
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 71776116913733615, v2: 0}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1073741824, v2: 0}, // X14
		},
	},
	{
		name:           "LoweredMoveLoop",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		needIntTemp:    true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers:     regMask{v1: 1073741824, v2: 0}, // X14
			clobbersArg0: true,
			clobbersArg1: true,
		},
	},
	{
		name:           "REPMOVSQ",
		argLen:         4,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 128, v2: 0}}, // DI
				{1, regMask{v1: 64, v2: 0}},  // SI
				{2, regMask{v1: 2, v2: 0}},   // CX
			},
			clobbers: regMask{v1: 194, v2: 0}, // CX SI DI
		},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:   "LoweredGetG",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // DX
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		clobberFlags:   true,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49151, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 71776116913668096, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 K1 K2 K3 K4 K5 K6 K7
			outputs: []outputInfo{
				{0, regMask{v1: 2048, v2: 0}}, // R11
			},
		},
	},
	{
		name:              "LoweredHasCPUFeature",
		auxType:           auxSym,
		argLen:            0,
		rematerializeable: true,
		symEffect:         SymNone,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:   "FlagEQ",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT_ULT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT_UGT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT_UGT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT_ULT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:           "MOVBatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVLatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AMOVL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVQatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XCHGB",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXCHGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XCHGL",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXCHGL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XCHGQ",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXCHGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XADDLlock",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXADDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "XADDQlock",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AXADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "AddTupleFirst32",
		argLen: 2,
		reg:    regInfo{},
	},
	{
		name:   "AddTupleFirst64",
		argLen: 2,
		reg:    regInfo{},
	},
	{
		name:           "CMPXCHGLlock",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.ACMPXCHGL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1, v2: 0}},     // AX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "CMPXCHGQlock",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.ACMPXCHGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1, v2: 0}},     // AX
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			clobbers: regMask{v1: 1, v2: 0}, // AX
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "ANDBlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ANDLlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ANDQlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORBlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AORB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORLlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "ORQlock",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:            "LoweredAtomicAnd64",
		auxType:         auxSymOff,
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		symEffect:       SymRdWr,
		asm:             x86.AANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:            "LoweredAtomicAnd32",
		auxType:         auxSymOff,
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		symEffect:       SymRdWr,
		asm:             x86.AANDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:            "LoweredAtomicOr64",
		auxType:         auxSymOff,
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		symEffect:       SymRdWr,
		asm:             x86.AORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:            "LoweredAtomicOr32",
		auxType:         auxSymOff,
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		symEffect:       SymRdWr,
		asm:             x86.AORL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49134, v2: 0}}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // AX
			},
		},
	},
	{
		name:           "PrefetchT0",
		argLen:         2,
		hasSideEffects: true,
		asm:            x86.APREFETCHT0,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "PrefetchNTA",
		argLen:         2,
		hasSideEffects: true,
		asm:            x86.APREFETCHNTA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "ANDNQ",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "ANDNL",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AANDNL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BLSIQ",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ABLSIQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BLSIL",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ABLSIL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BLSMSKQ",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ABLSMSKQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "BLSMSKL",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ABLSMSKL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "BLSRQ",
		argLen: 1,
		asm:    x86.ABLSRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "BLSRL",
		argLen: 1,
		asm:    x86.ABLSRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "TZCNTQ",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ATZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "TZCNTL",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ATZCNTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "LZCNTQ",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ALZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "LZCNTL",
		argLen:       1,
		clobberFlags: true,
		asm:          x86.ALZCNTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBEWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVBEW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVBELload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBEL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBELstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVBEL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:           "MOVBEQload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.AMOVBEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "MOVBEQstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            x86.AMOVBEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBELloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBEL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBELloadidx4",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBEL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBELloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBEL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBEQloadidx1",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBEQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBEQloadidx8",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          x86.AMOVBEQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "MOVBEWstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEW,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBEWstoreidx2",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEW,
		scale:        2,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBELstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEL,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBELstoreidx4",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEL,
		scale:        4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBELstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEL,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBEQstoreidx1",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEQ,
		scale:        1,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:         "MOVBEQstoreidx8",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          x86.AMOVBEQ,
		scale:        8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{2, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
		},
	},
	{
		name:   "SARXQ",
		argLen: 2,
		asm:    x86.ASARXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "SARXL",
		argLen: 2,
		asm:    x86.ASARXL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "SHLXQ",
		argLen: 2,
		asm:    x86.ASHLXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "SHLXL",
		argLen: 2,
		asm:    x86.ASHLXL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "SHRXQ",
		argLen: 2,
		asm:    x86.ASHRXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "SHRXL",
		argLen: 2,
		asm:    x86.ASHRXL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXLload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXQload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXLload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXQload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXLload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXQload",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXLloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXL,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXLloadidx4",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXL,
		scale:          4,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXLloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXL,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXQloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXQ,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SARXQloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASARXQ,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXLloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXL,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXLloadidx4",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXL,
		scale:          4,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXLloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXL,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXQloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXQ,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHLXQloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHLXQ,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXLloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXL,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXLloadidx4",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXL,
		scale:          4,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXLloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXL,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXQloadidx1",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXQ,
		scale:          1,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "SHRXQloadidx8",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            x86.ASHRXQ,
		scale:          8,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 49135, v2: 0}},             // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{1, regMask{v1: 49151, v2: 0}},             // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 72057594037993471, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:         "PUNPCKLBW",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.APUNPCKLBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "PSHUFLW",
		auxType: auxInt8,
		argLen:  1,
		asm:     x86.APSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "PSHUFBbroadcast",
		argLen:       1,
		resultInArg0: true,
		asm:          x86.APSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTB",
		argLen: 1,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "PSIGNB",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.APSIGNB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "PCMPEQB",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		asm:          x86.APCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "PMOVMSKB",
		argLen: 1,
		asm:    x86.APMOVMSKB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:           "VMOVDQUload128",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVDQUstore128",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VMOVDQUload256",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVDQUstore256",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VMOVDQUload512",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VMOVDQUstore512",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK32load128",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVPMASKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VPMASK32store128",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVPMASKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VPMASK64load128",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVPMASKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VPMASK64store128",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVPMASKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VPMASK32load256",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVPMASKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VPMASK32store256",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVPMASKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VPMASK64load256",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVPMASKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VPMASK64store256",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVPMASKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:           "VPMASK8load512",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK8store512",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK16load512",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK16store512",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK32load512",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK32store512",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK64load512",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:           "VPMASK64store512",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVMToVec8x16",
		argLen: 1,
		asm:    x86.AVPMOVM2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec8x32",
		argLen: 1,
		asm:    x86.AVPMOVM2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec8x64",
		argLen: 1,
		asm:    x86.AVPMOVM2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVMToVec16x8",
		argLen: 1,
		asm:    x86.AVPMOVM2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec16x16",
		argLen: 1,
		asm:    x86.AVPMOVM2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec16x32",
		argLen: 1,
		asm:    x86.AVPMOVM2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVMToVec32x4",
		argLen: 1,
		asm:    x86.AVPMOVM2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec32x8",
		argLen: 1,
		asm:    x86.AVPMOVM2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec32x16",
		argLen: 1,
		asm:    x86.AVPMOVM2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVMToVec64x2",
		argLen: 1,
		asm:    x86.AVPMOVM2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec64x4",
		argLen: 1,
		asm:    x86.AVPMOVM2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVMToVec64x8",
		argLen: 1,
		asm:    x86.AVPMOVM2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVVec8x16ToM",
		argLen: 1,
		asm:    x86.AVPMOVB2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec8x32ToM",
		argLen: 1,
		asm:    x86.AVPMOVB2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec8x64ToM",
		argLen: 1,
		asm:    x86.AVPMOVB2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec16x8ToM",
		argLen: 1,
		asm:    x86.AVPMOVW2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec16x16ToM",
		argLen: 1,
		asm:    x86.AVPMOVW2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec16x32ToM",
		argLen: 1,
		asm:    x86.AVPMOVW2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec32x4ToM",
		argLen: 1,
		asm:    x86.AVPMOVD2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec32x8ToM",
		argLen: 1,
		asm:    x86.AVPMOVD2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec32x16ToM",
		argLen: 1,
		asm:    x86.AVPMOVD2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec64x2ToM",
		argLen: 1,
		asm:    x86.AVPMOVQ2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec64x4ToM",
		argLen: 1,
		asm:    x86.AVPMOVQ2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVVec64x8ToM",
		argLen: 1,
		asm:    x86.AVPMOVQ2M,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPMOVMSKB128",
		argLen: 1,
		asm:    x86.AVPMOVMSKB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "VPMOVMSKB256",
		argLen: 1,
		asm:    x86.AVPMOVMSKB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "VMOVMSKPS128",
		argLen: 1,
		asm:    x86.AVMOVMSKPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "VMOVMSKPS256",
		argLen: 1,
		asm:    x86.AVMOVMSKPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "VMOVMSKPD128",
		argLen: 1,
		asm:    x86.AVMOVMSKPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "VMOVMSKPD256",
		argLen: 1,
		asm:    x86.AVMOVMSKPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:      "Zero128",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147483648, v2: 0}}, // X15
			},
		},
	},
	{
		name:   "Zero256",
		argLen: 0,
		asm:    x86.AVPXOR,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "Zero512",
		argLen: 0,
		asm:    x86.AVPXORQ,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVSDf2v",
		argLen: 1,
		asm:    x86.AVMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VMOVSSf2v",
		argLen: 1,
		asm:    x86.AVMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VMOVQ",
		argLen: 1,
		asm:    x86.AVMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VMOVD",
		argLen: 1,
		asm:    x86.AVMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVQload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVSSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:           "VMOVSDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AVMOVSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:              "VMOVSSconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		asm:               x86.AVMOVSS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:              "VMOVSDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		asm:               x86.AVMOVSD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VZEROUPPER",
		argLen: 1,
		asm:    x86.AVZEROUPPER,
		reg: regInfo{
			clobbers: regMask{v1: 2147418112, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
		},
	},
	{
		name:   "VZEROALL",
		argLen: 1,
		asm:    x86.AVZEROALL,
		reg: regInfo{
			clobbers: regMask{v1: 2147418112, v2: 0}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
		},
	},
	{
		name:           "KMOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AKMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:           "KMOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AKMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:           "KMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:           "KMOVQload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            x86.AKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:           "KMOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AKMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:           "KMOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AKMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:           "KMOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:           "KMOVQstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            x86.AKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
		},
	},
	{
		name:   "KMOVQk",
		argLen: 1,
		asm:    x86.AKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KMOVDk",
		argLen: 1,
		asm:    x86.AKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KMOVWk",
		argLen: 1,
		asm:    x86.AKMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KMOVBk",
		argLen: 1,
		asm:    x86.AKMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KMOVQi",
		argLen: 1,
		asm:    x86.AKMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "KMOVDi",
		argLen: 1,
		asm:    x86.AKMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "KMOVWi",
		argLen: 1,
		asm:    x86.AKMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "KMOVBi",
		argLen: 1,
		asm:    x86.AKMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:   "KANDB",
		argLen: 2,
		asm:    x86.AKANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KANDW",
		argLen: 2,
		asm:    x86.AKANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KANDD",
		argLen: 2,
		asm:    x86.AKANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KANDQ",
		argLen: 2,
		asm:    x86.AKANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KORB",
		argLen: 2,
		asm:    x86.AKORB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KORW",
		argLen: 2,
		asm:    x86.AKORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KORD",
		argLen: 2,
		asm:    x86.AKORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KORQ",
		argLen: 2,
		asm:    x86.AKORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXORB",
		argLen: 2,
		asm:    x86.AKXORB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXORW",
		argLen: 2,
		asm:    x86.AKXORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXORD",
		argLen: 2,
		asm:    x86.AKXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXORQ",
		argLen: 2,
		asm:    x86.AKXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXNORB",
		argLen: 2,
		asm:    x86.AKXNORB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXNORW",
		argLen: 2,
		asm:    x86.AKXNORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXNORD",
		argLen: 2,
		asm:    x86.AKXNORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "KXNORQ",
		argLen: 2,
		asm:    x86.AKXNORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:         "VPTEST",
		argLen:       2,
		clobberFlags: true,
		asm:          x86.AVPTEST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
		},
	},
	{
		name:         "SHA1MSG1128",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA1MSG1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SHA1MSG2128",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA1MSG2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SHA1NEXTE128",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA1NEXTE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SHA256MSG1128",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA256MSG1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SHA256MSG2128",
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA256MSG2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "SHA256RNDS2128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.ASHA256RNDS2,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 65536, v2: 0}},      // X0
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VADDPD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VADDPD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VADDPD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPS128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VADDPS256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VADDPS512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPSMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPSMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VADDPSMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VADDSUBPD128",
		argLen: 2,
		asm:    x86.AVADDSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VADDSUBPD256",
		argLen: 2,
		asm:    x86.AVADDSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VADDSUBPS128",
		argLen: 2,
		asm:    x86.AVADDSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VADDSUBPS256",
		argLen: 2,
		asm:    x86.AVADDSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESDEC128",
		argLen: 2,
		asm:    x86.AVAESDEC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESDEC256",
		argLen: 2,
		asm:    x86.AVAESDEC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESDEC512",
		argLen: 2,
		asm:    x86.AVAESDEC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VAESDECLAST128",
		argLen: 2,
		asm:    x86.AVAESDECLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESDECLAST256",
		argLen: 2,
		asm:    x86.AVAESDECLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESDECLAST512",
		argLen: 2,
		asm:    x86.AVAESDECLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VAESENC128",
		argLen: 2,
		asm:    x86.AVAESENC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESENC256",
		argLen: 2,
		asm:    x86.AVAESENC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESENC512",
		argLen: 2,
		asm:    x86.AVAESENC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VAESENCLAST128",
		argLen: 2,
		asm:    x86.AVAESENCLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESENCLAST256",
		argLen: 2,
		asm:    x86.AVAESENCLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VAESENCLAST512",
		argLen: 2,
		asm:    x86.AVAESENCLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VAESIMC128",
		argLen: 1,
		asm:    x86.AVAESIMC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VBROADCASTSD256",
		argLen: 1,
		asm:    x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VBROADCASTSD512",
		argLen: 1,
		asm:    x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSDMasked256",
		argLen: 2,
		asm:    x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSDMasked512",
		argLen: 2,
		asm:    x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSS128",
		argLen: 1,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VBROADCASTSS256",
		argLen: 1,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VBROADCASTSS512",
		argLen: 1,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSSMasked128",
		argLen: 2,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSSMasked256",
		argLen: 2,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VBROADCASTSSMasked512",
		argLen: 2,
		asm:    x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPDMasked128",
		argLen: 2,
		asm:    x86.AVCOMPRESSPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPDMasked256",
		argLen: 2,
		asm:    x86.AVCOMPRESSPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPDMasked512",
		argLen: 2,
		asm:    x86.AVCOMPRESSPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPSMasked128",
		argLen: 2,
		asm:    x86.AVCOMPRESSPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPSMasked256",
		argLen: 2,
		asm:    x86.AVCOMPRESSPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCOMPRESSPSMasked512",
		argLen: 2,
		asm:    x86.AVCOMPRESSPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PD256",
		argLen: 1,
		asm:    x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTDQ2PD512",
		argLen: 1,
		asm:    x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PDMasked256",
		argLen: 2,
		asm:    x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PDMasked512",
		argLen: 2,
		asm:    x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PS128",
		argLen: 1,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTDQ2PS256",
		argLen: 1,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTDQ2PS512",
		argLen: 1,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PSMasked128",
		argLen: 2,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PSMasked256",
		argLen: 2,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTDQ2PSMasked512",
		argLen: 2,
		asm:    x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPD2PS256",
		argLen: 1,
		asm:    x86.AVCVTPD2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPD2PSMasked256",
		argLen: 2,
		asm:    x86.AVCVTPD2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPD2PSX128",
		argLen: 1,
		asm:    x86.AVCVTPD2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTPD2PSXMasked128",
		argLen: 2,
		asm:    x86.AVCVTPD2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPD2PSY128",
		argLen: 1,
		asm:    x86.AVCVTPD2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTPD2PSYMasked128",
		argLen: 2,
		asm:    x86.AVCVTPD2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPS2PD256",
		argLen: 1,
		asm:    x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTPS2PD512",
		argLen: 1,
		asm:    x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPS2PDMasked256",
		argLen: 2,
		asm:    x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTPS2PDMasked512",
		argLen: 2,
		asm:    x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PD128",
		argLen: 1,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PD256",
		argLen: 1,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PD512",
		argLen: 1,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PDMasked128",
		argLen: 2,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PDMasked256",
		argLen: 2,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PDMasked512",
		argLen: 2,
		asm:    x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PS256",
		argLen: 1,
		asm:    x86.AVCVTQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PSMasked256",
		argLen: 2,
		asm:    x86.AVCVTQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PSX128",
		argLen: 1,
		asm:    x86.AVCVTQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PSXMasked128",
		argLen: 2,
		asm:    x86.AVCVTQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PSY128",
		argLen: 1,
		asm:    x86.AVCVTQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTQQ2PSYMasked128",
		argLen: 2,
		asm:    x86.AVCVTQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2DQ256",
		argLen: 1,
		asm:    x86.AVCVTTPD2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2DQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPD2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2DQX128",
		argLen: 1,
		asm:    x86.AVCVTTPD2DQX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTTPD2DQXMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2DQX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2DQY128",
		argLen: 1,
		asm:    x86.AVCVTTPD2DQY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTTPD2DQYMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2DQY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQ128",
		argLen: 1,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQ256",
		argLen: 1,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQ512",
		argLen: 1,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2QQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQ256",
		argLen: 1,
		asm:    x86.AVCVTTPD2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPD2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQX128",
		argLen: 1,
		asm:    x86.AVCVTTPD2UDQX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQXMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2UDQX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQY128",
		argLen: 1,
		asm:    x86.AVCVTTPD2UDQY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UDQYMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2UDQY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQ128",
		argLen: 1,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQ256",
		argLen: 1,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQ512",
		argLen: 1,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPD2UQQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2DQ128",
		argLen: 1,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTTPS2DQ256",
		argLen: 1,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VCVTTPS2DQ512",
		argLen: 1,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2DQMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2DQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2DQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2QQ256",
		argLen: 1,
		asm:    x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2QQ512",
		argLen: 1,
		asm:    x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2QQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2QQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQ128",
		argLen: 1,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQ256",
		argLen: 1,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQ512",
		argLen: 1,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQMasked128",
		argLen: 2,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UDQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UQQ256",
		argLen: 1,
		asm:    x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UQQ512",
		argLen: 1,
		asm:    x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UQQMasked256",
		argLen: 2,
		asm:    x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTTPS2UQQMasked512",
		argLen: 2,
		asm:    x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PD256",
		argLen: 1,
		asm:    x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PD512",
		argLen: 1,
		asm:    x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PDMasked256",
		argLen: 2,
		asm:    x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PDMasked512",
		argLen: 2,
		asm:    x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PS128",
		argLen: 1,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PS256",
		argLen: 1,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PS512",
		argLen: 1,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PSMasked128",
		argLen: 2,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PSMasked256",
		argLen: 2,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUDQ2PSMasked512",
		argLen: 2,
		asm:    x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PD128",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PD256",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PD512",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PDMasked128",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PDMasked256",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PDMasked512",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PS256",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PSMasked256",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PSX128",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PSXMasked128",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PSY128",
		argLen: 1,
		asm:    x86.AVCVTUQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VCVTUQQ2PSYMasked128",
		argLen: 2,
		asm:    x86.AVCVTUQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPD128",
		argLen: 2,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VDIVPD256",
		argLen: 2,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VDIVPD512",
		argLen: 2,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPDMasked128",
		argLen: 3,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPDMasked256",
		argLen: 3,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPDMasked512",
		argLen: 3,
		asm:    x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPS128",
		argLen: 2,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VDIVPS256",
		argLen: 2,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VDIVPS512",
		argLen: 2,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPSMasked128",
		argLen: 3,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPSMasked256",
		argLen: 3,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VDIVPSMasked512",
		argLen: 3,
		asm:    x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPDMasked128",
		argLen: 2,
		asm:    x86.AVEXPANDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPDMasked256",
		argLen: 2,
		asm:    x86.AVEXPANDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPDMasked512",
		argLen: 2,
		asm:    x86.AVEXPANDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPSMasked128",
		argLen: 2,
		asm:    x86.AVEXPANDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPSMasked256",
		argLen: 2,
		asm:    x86.AVEXPANDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VEXPANDPSMasked512",
		argLen: 2,
		asm:    x86.AVEXPANDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PS128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PS256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PS512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PS128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PS256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PS512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PS128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PS256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PS512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULB128",
		argLen: 2,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULB256",
		argLen: 2,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULB512",
		argLen: 2,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULBMasked128",
		argLen: 3,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULBMasked256",
		argLen: 3,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VGF2P8MULBMasked512",
		argLen: 3,
		asm:    x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VHADDPD128",
		argLen: 2,
		asm:    x86.AVHADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHADDPD256",
		argLen: 2,
		asm:    x86.AVHADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHADDPS128",
		argLen: 2,
		asm:    x86.AVHADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHADDPS256",
		argLen: 2,
		asm:    x86.AVHADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHSUBPD128",
		argLen: 2,
		asm:    x86.AVHSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHSUBPD256",
		argLen: 2,
		asm:    x86.AVHSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHSUBPS128",
		argLen: 2,
		asm:    x86.AVHSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VHSUBPS256",
		argLen: 2,
		asm:    x86.AVHSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMAXPD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMAXPD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMAXPD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPS128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMAXPS256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMAXPS512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPSMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPSMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMAXPSMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMINPD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMINPD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPS128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMINPS256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMINPS512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPSMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPSMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMINPSMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU8Masked128",
		argLen: 2,
		asm:    x86.AVMOVDQU8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU8Masked256",
		argLen: 2,
		asm:    x86.AVMOVDQU8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU8Masked512",
		argLen: 2,
		asm:    x86.AVMOVDQU8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU16Masked128",
		argLen: 2,
		asm:    x86.AVMOVDQU16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU16Masked256",
		argLen: 2,
		asm:    x86.AVMOVDQU16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU16Masked512",
		argLen: 2,
		asm:    x86.AVMOVDQU16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU32Masked128",
		argLen: 2,
		asm:    x86.AVMOVDQU32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU32Masked256",
		argLen: 2,
		asm:    x86.AVMOVDQU32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU32Masked512",
		argLen: 2,
		asm:    x86.AVMOVDQU32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU64Masked128",
		argLen: 2,
		asm:    x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU64Masked256",
		argLen: 2,
		asm:    x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VMOVDQU64Masked512",
		argLen: 2,
		asm:    x86.AVMOVDQU64,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMULPD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMULPD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPS128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMULPS256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VMULPS512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPSMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPSMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VMULPSMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSB128",
		argLen: 1,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSB256",
		argLen: 1,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSB512",
		argLen: 1,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSBMasked128",
		argLen: 2,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSBMasked256",
		argLen: 2,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSBMasked512",
		argLen: 2,
		asm:    x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSD128",
		argLen: 1,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSD256",
		argLen: 1,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSD512",
		argLen: 1,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSDMasked128",
		argLen: 2,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSDMasked256",
		argLen: 2,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSDMasked512",
		argLen: 2,
		asm:    x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQ128",
		argLen: 1,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQ256",
		argLen: 1,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQ512",
		argLen: 1,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQMasked128",
		argLen: 2,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQMasked256",
		argLen: 2,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSQMasked512",
		argLen: 2,
		asm:    x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSW128",
		argLen: 1,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSW256",
		argLen: 1,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPABSW512",
		argLen: 1,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSWMasked128",
		argLen: 2,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSWMasked256",
		argLen: 2,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPABSWMasked512",
		argLen: 2,
		asm:    x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKSSDW128",
		argLen: 2,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPACKSSDW256",
		argLen: 2,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPACKSSDW512",
		argLen: 2,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKSSDWMasked128",
		argLen: 3,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKSSDWMasked256",
		argLen: 3,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKSSDWMasked512",
		argLen: 3,
		asm:    x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKUSDW128",
		argLen: 2,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPACKUSDW256",
		argLen: 2,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPACKUSDW512",
		argLen: 2,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKUSDWMasked128",
		argLen: 3,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKUSDWMasked256",
		argLen: 3,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPACKUSDWMasked512",
		argLen: 3,
		asm:    x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDSB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDSB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDSW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDSW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDSWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDUSB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDUSB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDUSW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDUSW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDUSWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPADDW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPADDWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAND128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPAND256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPANDD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDN128",
		argLen: 2,
		asm:    x86.AVPANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPANDN256",
		argLen: 2,
		asm:    x86.AVPANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPANDND512",
		argLen: 2,
		asm:    x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNDMasked128",
		argLen: 3,
		asm:    x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNDMasked256",
		argLen: 3,
		asm:    x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNDMasked512",
		argLen: 3,
		asm:    x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNQ512",
		argLen: 2,
		asm:    x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNQMasked128",
		argLen: 3,
		asm:    x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNQMasked256",
		argLen: 3,
		asm:    x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPANDNQMasked512",
		argLen: 3,
		asm:    x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPANDQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPAVGB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPAVGB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPAVGW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPAVGW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPAVGWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBLENDMBMasked512",
		argLen: 3,
		asm:    x86.AVPBLENDMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBLENDMDMasked512",
		argLen: 3,
		asm:    x86.AVPBLENDMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBLENDMQMasked512",
		argLen: 3,
		asm:    x86.AVPBLENDMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBLENDMWMasked512",
		argLen: 3,
		asm:    x86.AVPBLENDMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBLENDVB128",
		argLen: 3,
		asm:    x86.AVPBLENDVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBLENDVB256",
		argLen: 3,
		asm:    x86.AVPBLENDVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTB128",
		argLen: 1,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTB256",
		argLen: 1,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTB512",
		argLen: 1,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTBMasked128",
		argLen: 2,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTBMasked256",
		argLen: 2,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTBMasked512",
		argLen: 2,
		asm:    x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTD128",
		argLen: 1,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTD256",
		argLen: 1,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTD512",
		argLen: 1,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTDMasked128",
		argLen: 2,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTDMasked256",
		argLen: 2,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTDMasked512",
		argLen: 2,
		asm:    x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTQ128",
		argLen: 1,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTQ256",
		argLen: 1,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTQ512",
		argLen: 1,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTQMasked128",
		argLen: 2,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTQMasked256",
		argLen: 2,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTQMasked512",
		argLen: 2,
		asm:    x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTW128",
		argLen: 1,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTW256",
		argLen: 1,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPBROADCASTW512",
		argLen: 1,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTWMasked128",
		argLen: 2,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTWMasked256",
		argLen: 2,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPBROADCASTWMasked512",
		argLen: 2,
		asm:    x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPCMPEQB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:        "VPCMPEQD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:        "VPCMPEQQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:        "VPCMPEQW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPCMPEQW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPCMPEQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPCMPGTB128",
		argLen: 2,
		asm:    x86.AVPCMPGTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTB256",
		argLen: 2,
		asm:    x86.AVPCMPGTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTB512",
		argLen: 2,
		asm:    x86.AVPCMPGTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPCMPGTD128",
		argLen: 2,
		asm:    x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTD256",
		argLen: 2,
		asm:    x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTD512",
		argLen: 2,
		asm:    x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPCMPGTQ128",
		argLen: 2,
		asm:    x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTQ256",
		argLen: 2,
		asm:    x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTQ512",
		argLen: 2,
		asm:    x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPCMPGTW128",
		argLen: 2,
		asm:    x86.AVPCMPGTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTW256",
		argLen: 2,
		asm:    x86.AVPCMPGTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPCMPGTW512",
		argLen: 2,
		asm:    x86.AVPCMPGTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:   "VPCOMPRESSBMasked128",
		argLen: 2,
		asm:    x86.AVPCOMPRESSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSBMasked256",
		argLen: 2,
		asm:    x86.AVPCOMPRESSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSBMasked512",
		argLen: 2,
		asm:    x86.AVPCOMPRESSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSDMasked128",
		argLen: 2,
		asm:    x86.AVPCOMPRESSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSDMasked256",
		argLen: 2,
		asm:    x86.AVPCOMPRESSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSDMasked512",
		argLen: 2,
		asm:    x86.AVPCOMPRESSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSQMasked128",
		argLen: 2,
		asm:    x86.AVPCOMPRESSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSQMasked256",
		argLen: 2,
		asm:    x86.AVPCOMPRESSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSQMasked512",
		argLen: 2,
		asm:    x86.AVPCOMPRESSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSWMasked128",
		argLen: 2,
		asm:    x86.AVPCOMPRESSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSWMasked256",
		argLen: 2,
		asm:    x86.AVPCOMPRESSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPCOMPRESSWMasked512",
		argLen: 2,
		asm:    x86.AVPCOMPRESSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPDPWSSD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPDPWSSD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMB128",
		argLen: 2,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMB256",
		argLen: 2,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMB512",
		argLen: 2,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMBMasked128",
		argLen: 3,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMBMasked256",
		argLen: 3,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMBMasked512",
		argLen: 3,
		asm:    x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMD256",
		argLen: 2,
		asm:    x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPERMD512",
		argLen: 2,
		asm:    x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMDMasked256",
		argLen: 3,
		asm:    x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMDMasked512",
		argLen: 3,
		asm:    x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2B128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2B256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2B512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2BMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2BMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2BMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2W128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2W256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2W512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2WMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2WMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2WMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPD256",
		argLen: 2,
		asm:    x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPD512",
		argLen: 2,
		asm:    x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPDMasked256",
		argLen: 3,
		asm:    x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPDMasked512",
		argLen: 3,
		asm:    x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPS256",
		argLen: 2,
		asm:    x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPERMPS512",
		argLen: 2,
		asm:    x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPSMasked256",
		argLen: 3,
		asm:    x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMPSMasked512",
		argLen: 3,
		asm:    x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMQ256",
		argLen: 2,
		asm:    x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMQ512",
		argLen: 2,
		asm:    x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMQMasked256",
		argLen: 3,
		asm:    x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMQMasked512",
		argLen: 3,
		asm:    x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMW128",
		argLen: 2,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMW256",
		argLen: 2,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMW512",
		argLen: 2,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMWMasked128",
		argLen: 3,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMWMasked256",
		argLen: 3,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPERMWMasked512",
		argLen: 3,
		asm:    x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDBMasked128",
		argLen: 2,
		asm:    x86.AVPEXPANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDBMasked256",
		argLen: 2,
		asm:    x86.AVPEXPANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDBMasked512",
		argLen: 2,
		asm:    x86.AVPEXPANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDDMasked128",
		argLen: 2,
		asm:    x86.AVPEXPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDDMasked256",
		argLen: 2,
		asm:    x86.AVPEXPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDDMasked512",
		argLen: 2,
		asm:    x86.AVPEXPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDQMasked128",
		argLen: 2,
		asm:    x86.AVPEXPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDQMasked256",
		argLen: 2,
		asm:    x86.AVPEXPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDQMasked512",
		argLen: 2,
		asm:    x86.AVPEXPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDWMasked128",
		argLen: 2,
		asm:    x86.AVPEXPANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDWMasked256",
		argLen: 2,
		asm:    x86.AVPEXPANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPEXPANDWMasked512",
		argLen: 2,
		asm:    x86.AVPEXPANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPHADDD128",
		argLen: 2,
		asm:    x86.AVPHADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHADDD256",
		argLen: 2,
		asm:    x86.AVPHADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHADDSW128",
		argLen: 2,
		asm:    x86.AVPHADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHADDSW256",
		argLen: 2,
		asm:    x86.AVPHADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHADDW128",
		argLen: 2,
		asm:    x86.AVPHADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHADDW256",
		argLen: 2,
		asm:    x86.AVPHADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBD128",
		argLen: 2,
		asm:    x86.AVPHSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBD256",
		argLen: 2,
		asm:    x86.AVPHSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBSW128",
		argLen: 2,
		asm:    x86.AVPHSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBSW256",
		argLen: 2,
		asm:    x86.AVPHSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBW128",
		argLen: 2,
		asm:    x86.AVPHSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPHSUBW256",
		argLen: 2,
		asm:    x86.AVPHSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPLZCNTD128",
		argLen: 1,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTD256",
		argLen: 1,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTD512",
		argLen: 1,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTDMasked128",
		argLen: 2,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTDMasked256",
		argLen: 2,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTDMasked512",
		argLen: 2,
		asm:    x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQ128",
		argLen: 1,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQ256",
		argLen: 1,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQ512",
		argLen: 1,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQMasked128",
		argLen: 2,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQMasked256",
		argLen: 2,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPLZCNTQMasked512",
		argLen: 2,
		asm:    x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDUBSW128",
		argLen: 2,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMADDUBSW256",
		argLen: 2,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMADDUBSW512",
		argLen: 2,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDUBSWMasked128",
		argLen: 3,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDUBSWMasked256",
		argLen: 3,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDUBSWMasked512",
		argLen: 3,
		asm:    x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDWD128",
		argLen: 2,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMADDWD256",
		argLen: 2,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMADDWD512",
		argLen: 2,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDWDMasked128",
		argLen: 3,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDWDMasked256",
		argLen: 3,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMADDWDMasked512",
		argLen: 3,
		asm:    x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXSW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXSWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMAXUW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMAXUWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINSW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINSWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUB128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUB256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUB512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUBMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUBMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUBMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMINUW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMINUWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDB128_128",
		argLen: 1,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDB128_256",
		argLen: 1,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDB128_512",
		argLen: 1,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDW128_128",
		argLen: 1,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDW128_256",
		argLen: 1,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDW256",
		argLen: 1,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVDWMasked256",
		argLen: 2,
		asm:    x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQB128_128",
		argLen: 1,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQB128_256",
		argLen: 1,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQB128_512",
		argLen: 1,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQD128_128",
		argLen: 1,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQD128_256",
		argLen: 1,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQD256",
		argLen: 1,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQDMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQDMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQW128_128",
		argLen: 1,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQW128_256",
		argLen: 1,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQW128_512",
		argLen: 1,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVQWMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDB128_128",
		argLen: 1,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDB128_256",
		argLen: 1,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDB128_512",
		argLen: 1,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDW128_128",
		argLen: 1,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDW128_256",
		argLen: 1,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDW256",
		argLen: 1,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSDWMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQB128_128",
		argLen: 1,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQB128_256",
		argLen: 1,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQB128_512",
		argLen: 1,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQD128_128",
		argLen: 1,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQD128_256",
		argLen: 1,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQD256",
		argLen: 1,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQDMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQDMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQW128_128",
		argLen: 1,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQW128_256",
		argLen: 1,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQW128_512",
		argLen: 1,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSQWMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWB128_128",
		argLen: 1,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWB128_256",
		argLen: 1,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWB256",
		argLen: 1,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSWBMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBD128",
		argLen: 1,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBD256",
		argLen: 1,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBD512",
		argLen: 1,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBDMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBDMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBQ128",
		argLen: 1,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBQ256",
		argLen: 1,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBQ512",
		argLen: 1,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBW128",
		argLen: 1,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBW256",
		argLen: 1,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXBW512",
		argLen: 1,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBWMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBWMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXBWMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXDQ128",
		argLen: 1,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXDQ256",
		argLen: 1,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXDQ512",
		argLen: 1,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXDQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXDQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXDQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWD128",
		argLen: 1,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXWD256",
		argLen: 1,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXWD512",
		argLen: 1,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWDMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWDMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWQ128",
		argLen: 1,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXWQ256",
		argLen: 1,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVSXWQ512",
		argLen: 1,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVSXWQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDB128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDB128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDB128_512",
		argLen: 1,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDW128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDW128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDW256",
		argLen: 1,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSDWMasked256",
		argLen: 2,
		asm:    x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQB128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQB128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQB128_512",
		argLen: 1,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQBMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQD128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQD128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQD256",
		argLen: 1,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQDMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQDMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQW128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQW128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQW128_512",
		argLen: 1,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQWMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQWMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSQWMasked128_512",
		argLen: 2,
		asm:    x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWB128_128",
		argLen: 1,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWB128_256",
		argLen: 1,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWB256",
		argLen: 1,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVUSWBMasked256",
		argLen: 2,
		asm:    x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWB128_128",
		argLen: 1,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWB128_256",
		argLen: 1,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWB256",
		argLen: 1,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWBMasked128_128",
		argLen: 2,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWBMasked128_256",
		argLen: 2,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVWBMasked256",
		argLen: 2,
		asm:    x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBD128",
		argLen: 1,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBD256",
		argLen: 1,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBD512",
		argLen: 1,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBDMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBDMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBQ128",
		argLen: 1,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBQ256",
		argLen: 1,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBQ512",
		argLen: 1,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBW128",
		argLen: 1,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBW256",
		argLen: 1,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXBW512",
		argLen: 1,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBWMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBWMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXBWMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXDQ128",
		argLen: 1,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXDQ256",
		argLen: 1,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXDQ512",
		argLen: 1,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXDQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXDQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXDQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWD128",
		argLen: 1,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXWD256",
		argLen: 1,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXWD512",
		argLen: 1,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWDMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWDMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWDMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWQ128",
		argLen: 1,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXWQ256",
		argLen: 1,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPMOVZXWQ512",
		argLen: 1,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWQMasked128",
		argLen: 2,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWQMasked256",
		argLen: 2,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPMOVZXWQMasked512",
		argLen: 2,
		asm:    x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULDQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULDQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULHUW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULHUW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULHUW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHUWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHUWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHUWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULHW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULHW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULHWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLD128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULLD256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULLD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLW128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULLW256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULLW512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLWMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLWMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULLWMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPMULUDQ128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULUDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPMULUDQ256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPMULUDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPOPCNTB128",
		argLen: 1,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTB256",
		argLen: 1,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTB512",
		argLen: 1,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTBMasked128",
		argLen: 2,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTBMasked256",
		argLen: 2,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTBMasked512",
		argLen: 2,
		asm:    x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTD128",
		argLen: 1,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTD256",
		argLen: 1,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTD512",
		argLen: 1,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTDMasked128",
		argLen: 2,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTDMasked256",
		argLen: 2,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTDMasked512",
		argLen: 2,
		asm:    x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQ128",
		argLen: 1,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQ256",
		argLen: 1,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQ512",
		argLen: 1,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQMasked128",
		argLen: 2,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQMasked256",
		argLen: 2,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTQMasked512",
		argLen: 2,
		asm:    x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTW128",
		argLen: 1,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTW256",
		argLen: 1,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTW512",
		argLen: 1,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTWMasked128",
		argLen: 2,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTWMasked256",
		argLen: 2,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPOPCNTWMasked512",
		argLen: 2,
		asm:    x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPOR128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPOR256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPORD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPORQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVD128",
		argLen: 2,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVD256",
		argLen: 2,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVD512",
		argLen: 2,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVDMasked128",
		argLen: 3,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVDMasked256",
		argLen: 3,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVDMasked512",
		argLen: 3,
		asm:    x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQ128",
		argLen: 2,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQ256",
		argLen: 2,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQ512",
		argLen: 2,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQMasked128",
		argLen: 3,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQMasked256",
		argLen: 3,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPROLVQMasked512",
		argLen: 3,
		asm:    x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVD128",
		argLen: 2,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVD256",
		argLen: 2,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVD512",
		argLen: 2,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVDMasked128",
		argLen: 3,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVDMasked256",
		argLen: 3,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVDMasked512",
		argLen: 3,
		asm:    x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQ128",
		argLen: 2,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQ256",
		argLen: 2,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQ512",
		argLen: 2,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQMasked128",
		argLen: 3,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQMasked256",
		argLen: 3,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPRORVQMasked512",
		argLen: 3,
		asm:    x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSADBW128",
		argLen: 2,
		asm:    x86.AVPSADBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSADBW256",
		argLen: 2,
		asm:    x86.AVPSADBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSADBW512",
		argLen: 2,
		asm:    x86.AVPSADBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVW128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVW256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVW512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVWMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVWMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVWMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVW128",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVW256",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVW512",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVWMasked128",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVWMasked256",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVWMasked512",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSHUFB128",
		argLen: 2,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSHUFB256",
		argLen: 2,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSHUFB512",
		argLen: 2,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSHUFBMasked128",
		argLen: 3,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSHUFBMasked256",
		argLen: 3,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSHUFBMasked512",
		argLen: 3,
		asm:    x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSIGNB128",
		argLen: 2,
		asm:    x86.AVPSIGNB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSIGNB256",
		argLen: 2,
		asm:    x86.AVPSIGNB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSIGND128",
		argLen: 2,
		asm:    x86.AVPSIGND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSIGND256",
		argLen: 2,
		asm:    x86.AVPSIGND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSIGNW128",
		argLen: 2,
		asm:    x86.AVPSIGNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSIGNW256",
		argLen: 2,
		asm:    x86.AVPSIGNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLD128",
		argLen: 2,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLD256",
		argLen: 2,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLD512",
		argLen: 2,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLDMasked128",
		argLen: 3,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLDMasked256",
		argLen: 3,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLDMasked512",
		argLen: 3,
		asm:    x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLQ128",
		argLen: 2,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLQ256",
		argLen: 2,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLQ512",
		argLen: 2,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLQMasked128",
		argLen: 3,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLQMasked256",
		argLen: 3,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLQMasked512",
		argLen: 3,
		asm:    x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVD128",
		argLen: 2,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLVD256",
		argLen: 2,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLVD512",
		argLen: 2,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVDMasked128",
		argLen: 3,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVDMasked256",
		argLen: 3,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVDMasked512",
		argLen: 3,
		asm:    x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVQ128",
		argLen: 2,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLVQ256",
		argLen: 2,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLVQ512",
		argLen: 2,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVQMasked128",
		argLen: 3,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVQMasked256",
		argLen: 3,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVQMasked512",
		argLen: 3,
		asm:    x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVW128",
		argLen: 2,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVW256",
		argLen: 2,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVW512",
		argLen: 2,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVWMasked128",
		argLen: 3,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVWMasked256",
		argLen: 3,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLVWMasked512",
		argLen: 3,
		asm:    x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLW128",
		argLen: 2,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLW256",
		argLen: 2,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSLLW512",
		argLen: 2,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLWMasked128",
		argLen: 3,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLWMasked256",
		argLen: 3,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSLLWMasked512",
		argLen: 3,
		asm:    x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAD128",
		argLen: 2,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAD256",
		argLen: 2,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAD512",
		argLen: 2,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRADMasked128",
		argLen: 3,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRADMasked256",
		argLen: 3,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRADMasked512",
		argLen: 3,
		asm:    x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQ128",
		argLen: 2,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQ256",
		argLen: 2,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQ512",
		argLen: 2,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQMasked128",
		argLen: 3,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQMasked256",
		argLen: 3,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAQMasked512",
		argLen: 3,
		asm:    x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVD128",
		argLen: 2,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAVD256",
		argLen: 2,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAVD512",
		argLen: 2,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVDMasked128",
		argLen: 3,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVDMasked256",
		argLen: 3,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVDMasked512",
		argLen: 3,
		asm:    x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQ128",
		argLen: 2,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQ256",
		argLen: 2,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQ512",
		argLen: 2,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQMasked128",
		argLen: 3,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQMasked256",
		argLen: 3,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVQMasked512",
		argLen: 3,
		asm:    x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVW128",
		argLen: 2,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVW256",
		argLen: 2,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVW512",
		argLen: 2,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVWMasked128",
		argLen: 3,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVWMasked256",
		argLen: 3,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAVWMasked512",
		argLen: 3,
		asm:    x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAW128",
		argLen: 2,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAW256",
		argLen: 2,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRAW512",
		argLen: 2,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAWMasked128",
		argLen: 3,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAWMasked256",
		argLen: 3,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRAWMasked512",
		argLen: 3,
		asm:    x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLD128",
		argLen: 2,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLD256",
		argLen: 2,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLD512",
		argLen: 2,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLDMasked128",
		argLen: 3,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLDMasked256",
		argLen: 3,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLDMasked512",
		argLen: 3,
		asm:    x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLQ128",
		argLen: 2,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLQ256",
		argLen: 2,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLQ512",
		argLen: 2,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLQMasked128",
		argLen: 3,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLQMasked256",
		argLen: 3,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLQMasked512",
		argLen: 3,
		asm:    x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVD128",
		argLen: 2,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLVD256",
		argLen: 2,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLVD512",
		argLen: 2,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVDMasked128",
		argLen: 3,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVDMasked256",
		argLen: 3,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVDMasked512",
		argLen: 3,
		asm:    x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVQ128",
		argLen: 2,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLVQ256",
		argLen: 2,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLVQ512",
		argLen: 2,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVQMasked128",
		argLen: 3,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVQMasked256",
		argLen: 3,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVQMasked512",
		argLen: 3,
		asm:    x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVW128",
		argLen: 2,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVW256",
		argLen: 2,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVW512",
		argLen: 2,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVWMasked128",
		argLen: 3,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVWMasked256",
		argLen: 3,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLVWMasked512",
		argLen: 3,
		asm:    x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLW128",
		argLen: 2,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLW256",
		argLen: 2,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSRLW512",
		argLen: 2,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2147418112, v2: 0}},      // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLWMasked128",
		argLen: 3,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLWMasked256",
		argLen: 3,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSRLWMasked512",
		argLen: 3,
		asm:    x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBB128",
		argLen: 2,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBB256",
		argLen: 2,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBB512",
		argLen: 2,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBBMasked128",
		argLen: 3,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBBMasked256",
		argLen: 3,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBBMasked512",
		argLen: 3,
		asm:    x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBD128",
		argLen: 2,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBD256",
		argLen: 2,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBD512",
		argLen: 2,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBDMasked128",
		argLen: 3,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBDMasked256",
		argLen: 3,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBDMasked512",
		argLen: 3,
		asm:    x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBQ128",
		argLen: 2,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBQ256",
		argLen: 2,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBQ512",
		argLen: 2,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBQMasked128",
		argLen: 3,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBQMasked256",
		argLen: 3,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBQMasked512",
		argLen: 3,
		asm:    x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSB128",
		argLen: 2,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBSB256",
		argLen: 2,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBSB512",
		argLen: 2,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSBMasked128",
		argLen: 3,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSBMasked256",
		argLen: 3,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSBMasked512",
		argLen: 3,
		asm:    x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSW128",
		argLen: 2,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBSW256",
		argLen: 2,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBSW512",
		argLen: 2,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSWMasked128",
		argLen: 3,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSWMasked256",
		argLen: 3,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBSWMasked512",
		argLen: 3,
		asm:    x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSB128",
		argLen: 2,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBUSB256",
		argLen: 2,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBUSB512",
		argLen: 2,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSBMasked128",
		argLen: 3,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSBMasked256",
		argLen: 3,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSBMasked512",
		argLen: 3,
		asm:    x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSW128",
		argLen: 2,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBUSW256",
		argLen: 2,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBUSW512",
		argLen: 2,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSWMasked128",
		argLen: 3,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSWMasked256",
		argLen: 3,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBUSWMasked512",
		argLen: 3,
		asm:    x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBW128",
		argLen: 2,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBW256",
		argLen: 2,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPSUBW512",
		argLen: 2,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBWMasked128",
		argLen: 3,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBWMasked256",
		argLen: 3,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPSUBWMasked512",
		argLen: 3,
		asm:    x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKHDQ128",
		argLen: 2,
		asm:    x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHDQ256",
		argLen: 2,
		asm:    x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHDQ512",
		argLen: 2,
		asm:    x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKHQDQ128",
		argLen: 2,
		asm:    x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHQDQ256",
		argLen: 2,
		asm:    x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHQDQ512",
		argLen: 2,
		asm:    x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKHWD128",
		argLen: 2,
		asm:    x86.AVPUNPCKHWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHWD256",
		argLen: 2,
		asm:    x86.AVPUNPCKHWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKHWD512",
		argLen: 2,
		asm:    x86.AVPUNPCKHWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKLDQ128",
		argLen: 2,
		asm:    x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLDQ256",
		argLen: 2,
		asm:    x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLDQ512",
		argLen: 2,
		asm:    x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKLQDQ128",
		argLen: 2,
		asm:    x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLQDQ256",
		argLen: 2,
		asm:    x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLQDQ512",
		argLen: 2,
		asm:    x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VPUNPCKLWD128",
		argLen: 2,
		asm:    x86.AVPUNPCKLWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLWD256",
		argLen: 2,
		asm:    x86.AVPUNPCKLWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VPUNPCKLWD512",
		argLen: 2,
		asm:    x86.AVPUNPCKLWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXOR128",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPXOR256",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:        "VPXORD512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORDMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORDMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORDMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORQ512",
		argLen:      2,
		commutative: true,
		asm:         x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORQMasked128",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORQMasked256",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:        "VPXORQMasked512",
		argLen:      3,
		commutative: true,
		asm:         x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PD128",
		argLen: 1,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PD256",
		argLen: 1,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PD512",
		argLen: 1,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PDMasked128",
		argLen: 2,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PDMasked256",
		argLen: 2,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PDMasked512",
		argLen: 2,
		asm:    x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PS512",
		argLen: 1,
		asm:    x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PSMasked128",
		argLen: 2,
		asm:    x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PSMasked256",
		argLen: 2,
		asm:    x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCP14PSMasked512",
		argLen: 2,
		asm:    x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRCPPS128",
		argLen: 1,
		asm:    x86.AVRCPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VRCPPS256",
		argLen: 1,
		asm:    x86.AVRCPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VRSQRT14PD128",
		argLen: 1,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PD256",
		argLen: 1,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PD512",
		argLen: 1,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PDMasked128",
		argLen: 2,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PDMasked256",
		argLen: 2,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PDMasked512",
		argLen: 2,
		asm:    x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PS512",
		argLen: 1,
		asm:    x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PSMasked128",
		argLen: 2,
		asm:    x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PSMasked256",
		argLen: 2,
		asm:    x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRT14PSMasked512",
		argLen: 2,
		asm:    x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VRSQRTPS128",
		argLen: 1,
		asm:    x86.AVRSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VRSQRTPS256",
		argLen: 1,
		asm:    x86.AVRSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSCALEFPD128",
		argLen: 2,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPD256",
		argLen: 2,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPD512",
		argLen: 2,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPDMasked128",
		argLen: 3,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPDMasked256",
		argLen: 3,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPDMasked512",
		argLen: 3,
		asm:    x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPS128",
		argLen: 2,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPS256",
		argLen: 2,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPS512",
		argLen: 2,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPSMasked128",
		argLen: 3,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPSMasked256",
		argLen: 3,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSCALEFPSMasked512",
		argLen: 3,
		asm:    x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPD128",
		argLen: 1,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSQRTPD256",
		argLen: 1,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSQRTPD512",
		argLen: 1,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPDMasked128",
		argLen: 2,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPDMasked256",
		argLen: 2,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPDMasked512",
		argLen: 2,
		asm:    x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPS128",
		argLen: 1,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSQRTPS256",
		argLen: 1,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSQRTPS512",
		argLen: 1,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPSMasked128",
		argLen: 2,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPSMasked256",
		argLen: 2,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSQRTPSMasked512",
		argLen: 2,
		asm:    x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPD128",
		argLen: 2,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSUBPD256",
		argLen: 2,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSUBPD512",
		argLen: 2,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPDMasked128",
		argLen: 3,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPDMasked256",
		argLen: 3,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPDMasked512",
		argLen: 3,
		asm:    x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPS128",
		argLen: 2,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSUBPS256",
		argLen: 2,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:   "VSUBPS512",
		argLen: 2,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPSMasked128",
		argLen: 3,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPSMasked256",
		argLen: 3,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:   "VSUBPSMasked512",
		argLen: 3,
		asm:    x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "SHA1RNDS4128",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          x86.ASHA1RNDS4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VAESKEYGENASSIST128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVAESKEYGENASSIST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VCMPPD128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VCMPPD256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VCMPPD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPDMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPDMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPDMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPS128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VCMPPS256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VCMPPS512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPSMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPSMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VCMPPSMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VEXTRACTF64X4256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVEXTRACTF64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VEXTRACTF128128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVEXTRACTF128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VEXTRACTI64X4256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVEXTRACTI64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VEXTRACTI128128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVEXTRACTI128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQB128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQB256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQB512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQBMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQBMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEINVQBMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQB128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQB256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQB512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQBMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQBMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VGF2P8AFFINEQBMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VINSERTF64X4512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVINSERTF64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VINSERTF128256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVINSERTF128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VINSERTI64X4512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVINSERTI64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VINSERTI128256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVINSERTI128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPALIGNR128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPALIGNR256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPALIGNR512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPALIGNRMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPALIGNRMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPALIGNRMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPCLMULQDQ128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCLMULQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPCLMULQDQ256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCLMULQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPCLMULQDQ512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCLMULQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPCMPB512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPBMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPBMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPBMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPDMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPDMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPDMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPQ512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPQMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPQMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPQMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUB512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUBMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUBMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUBMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUDMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUDMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUDMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUQ512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUQMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUQMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUQMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUW512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUWMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUWMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPUWMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPW512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPWMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPWMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPCMPWMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:    "VPERM2F128256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPERM2F128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPERM2I128256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPERM2I128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPEXTRB128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPEXTRB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "VPEXTRD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPEXTRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "VPEXTRQ128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPEXTRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "VPEXTRW128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPEXTRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 49135, v2: 0}}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
			},
		},
	},
	{
		name:    "VPINSRB128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPINSRB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPINSRD128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPINSRD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPINSRQ128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPINSRQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPINSRW128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPINSRW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 49135, v2: 0}},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
				{0, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPROLD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLD512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLDMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLDMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLDMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQ128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQ256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQ512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPROLQMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORD512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORDMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORDMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORDMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQ128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQ256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQ512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPRORQMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDD128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDD256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDDMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDDMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDDMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQ128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQ256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQ512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDQMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDW128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDW256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDW512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDWMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDWMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHLDWMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDD128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDD256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDDMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDDMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDDMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQ128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQ256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQ512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDQMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDW128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDW256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDW512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDWMasked128",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDWMasked256",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHRDWMasked512",
		auxType: auxUInt8,
		argLen:  3,
		asm:     x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFD512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFDMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFDMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFDMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFHW128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFHW256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFHW512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFHWMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFHWMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFHWMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFLW128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFLW256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSHUFLW512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFLWMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFLWMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSHUFLWMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLD128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLD256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLD512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLDMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLDMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLDMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLQ128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLQ256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLQ512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLQMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLQMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLQMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLW128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLW256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSLLW512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLWMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLWMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSLLWMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAD128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRAD256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRAD512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRADMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRADMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRADMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQ128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQ256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQ512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAQMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAW128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRAW256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRAW512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAWMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAWMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRAWMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLD128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLD256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLD512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLDMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLDMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLDMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLQ128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLQ256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLQ512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLQMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLQMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLQMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLW128const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLW256const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VPSRLW512const",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLWMasked128const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLWMasked256const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VPSRLWMasked512const",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD128",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD256",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD512",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ128",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ256",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ512",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPD512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPDMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPDMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPDMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPS128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPS256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPS512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPSMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPSMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VREDUCEPSMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPD512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPDMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPDMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPDMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPS128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPS256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPS512",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPSMasked128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPSMasked256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VRNDSCALEPSMasked512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VROUNDPD128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVROUNDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VROUNDPD256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVROUNDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VROUNDPS128",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVROUNDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VROUNDPS256",
		auxType: auxUInt8,
		argLen:  1,
		asm:     x86.AVROUNDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VSHUFPD128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VSHUFPD256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VSHUFPD512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:    "VSHUFPS128",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VSHUFPS256",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:    "VSHUFPS512",
		auxType: auxUInt8,
		argLen:  2,
		asm:     x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VADDSUBPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDSUBPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDSUBPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VADDSUBPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVADDSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESDEC128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESDEC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESDEC256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESDEC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESDECLAST128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESDECLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESDECLAST256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESDECLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESENC128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESENC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESENC256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESENC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESENCLAST128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESENCLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESENCLAST256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVAESENCLAST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VAESIMC128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVAESIMC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VBROADCASTSD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VBROADCASTSD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VBROADCASTSS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VBROADCASTSS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VBROADCASTSSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTDQ2PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTDQ2PS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTDQ2PS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTDQ2PSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPD2PS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPD2PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPD2PSX128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTPD2PSXMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPD2PSY128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTPD2PSYMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTPD2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPS2PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTPS2PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPS2PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTPS2PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PSX128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PSXMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PSY128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTQQ2PSYMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2DQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2DQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2DQX128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTTPD2DQXMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2DQY128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTTPD2DQYMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2DQY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2QQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQX128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQXMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQY128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UDQYMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UDQY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPD2UQQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2DQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTTPS2DQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCVTTPS2DQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2DQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2DQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2DQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2QQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2QQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2QQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2QQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UDQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UQQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UQQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UQQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTTPS2UQQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUDQ2PSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PSX128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PSXMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PSY128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VCVTUQQ2PSYMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCVTUQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VDIVPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VDIVPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VDIVPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VDIVPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VDIVPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VEXPANDPDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVEXPANDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VEXPANDPDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVEXPANDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VEXPANDPSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVEXPANDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VEXPANDPSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVEXPANDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PS128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PS256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADD213PS512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADD213PSMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PS128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PS256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMADDSUB213PS512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMADDSUB213PSMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMADDSUB213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PS128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PS256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VFMSUBADD213PS512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VFMSUBADD213PSMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVFMSUBADD213PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8MULB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8MULB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8MULBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8MULBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VHADDPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHADDPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHADDPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHADDPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHSUBPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHSUBPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHSUBPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VHSUBPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVHSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMAXPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMAXPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMAXPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMAXPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMAXPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMAXPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMINPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMINPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMINPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMINPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMINPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMULPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMULPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMULPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VMULPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VMULPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSB128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSB256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSBMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSBMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSW128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSW256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPABSWMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPABSWMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKSSDW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPACKSSDW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPACKSSDW512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKSSDWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKSSDWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKSSDWMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKUSDW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPACKUSDW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPACKUSDW512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKUSDWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKUSDWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPACKUSDWMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDUSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDUSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDUSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDUSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDUSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDUSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDUSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDUSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPADDWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPADDWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPAND128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPAND256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPANDD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDN128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPANDN256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPANDND512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDND,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDNQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDNQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPANDQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPAVGB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPAVGB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPAVGBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPAVGBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPAVGW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPAVGW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPAVGWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPAVGWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBLENDMDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPBLENDMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBLENDMQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPBLENDMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTB128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTB256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTB512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTBMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTBMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTBMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPBROADCASTW128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPBROADCASTW256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPEQQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPEQW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPEQW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPEQW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPGTQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPGTW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCMPGTW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPGTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPDPWSSD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPDPWSSD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 4294901760, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPDPWSSD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPDPWSSDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPDPWSSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPERMD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2B128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2B256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2BMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2BMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2B,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2D512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2DMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2D,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PS512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2PSMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2Q512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2QMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2Q,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2W128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2W256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2WMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPERMI2WMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPERMI2W,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPERMPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPERMWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPERMW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDBMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDBMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDWMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPEXPANDWMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPEXPANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPHADDD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHADDD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHADDSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHADDSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHADDW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHADDW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPHSUBW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPHSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPLZCNTD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPLZCNTQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMADDUBSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMADDUBSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMADDUBSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMADDUBSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMADDWD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMADDWD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMADDWDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMADDWDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMAXUWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMAXUWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMINUWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMINUWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBW128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBW256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXBW512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBWMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBWMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXBWMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXDQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXDQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXDQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXDQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXDQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXDQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXWD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXWD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXWQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVSXWQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVSXWQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBW128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBW256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXBW512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBWMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBWMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXBWMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXDQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXDQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXDQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXDQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXDQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXDQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXWD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXWD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXWQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMOVZXWQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMOVZXWQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULHUW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULHUW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULHUWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULHUWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULHW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULHW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULHWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULHWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULLD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULLD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULLW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULLWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULLWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPMULUDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULUDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPMULUDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPMULUDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPOPCNTB128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTB256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTBMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTBMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQ128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQ256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQ512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTQMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTW128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTW256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTWMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOPCNTWMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPOR128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPOR256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPORD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPORQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLVQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORVQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSADBW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSADBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSADBW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSADBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:         "VPSHLDVD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQ512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVQMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVW128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVW256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVWMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHLDVWMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHLDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVD512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVDMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQ512load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVQMasked512load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVW128load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVW256load",
		auxType:      auxSymOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVWMasked128load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHRDVWMasked256load",
		auxType:      auxSymOff,
		argLen:       5,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPSHRDVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSIGNB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGNB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSIGNB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGNB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSIGND128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSIGND256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSIGNW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSIGNW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSIGNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSLLVD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSLLVD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSLLVD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSLLVQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSLLVQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLVWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRAVD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRAVD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAVWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRLVD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRLVD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRLVQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSRLVQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLVWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBUSB128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBUSB256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBUSBMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBUSBMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBUSW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBUSW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBUSWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBUSWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBW128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBW256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSUBWMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSUBWMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPUNPCKHDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKHDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKHDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPUNPCKHQDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKHQDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKHQDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPUNPCKHWD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKHWD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKHWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPUNPCKLQDQ128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLQDQ256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLQDQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPUNPCKLWD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPUNPCKLWD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPUNPCKLWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPXOR128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPXOR256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPXORD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORQ512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORQMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORQMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPXORQMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCP14PSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRCPPS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VRCPPS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRCPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VRSQRT14PD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRT14PSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRSQRTPS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VRSQRTPS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSCALEFPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSCALEFPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPD128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSQRTPD256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSQRTPD512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPDMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPDMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPDMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPS128load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSQRTPS256load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSQRTPS512load",
		auxType:   auxSymOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPSMasked128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPSMasked256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSQRTPSMasked512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPD128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSUBPD256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSUBPD512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPDMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPDMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPDMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPS128load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSUBPS256load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSUBPS512load",
		auxType:   auxSymOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPSMasked128load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPSMasked256load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSUBPSMasked512load",
		auxType:   auxSymOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VAESKEYGENASSIST128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVAESKEYGENASSIST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCMPPD128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCMPPD256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCMPPD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPS128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCMPPS256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VCMPPS512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPSMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPSMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VCMPPSMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVCMPPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQB128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQB256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQB512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQBMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQBMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEINVQBMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEINVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQB128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQB256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQB512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQBMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQBMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VGF2P8AFFINEQBMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVGF2P8AFFINEQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VINSERTF64X4512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVINSERTF64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VINSERTF128256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVINSERTF128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VINSERTI64X4512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVINSERTI64X4,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VINSERTI128256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVINSERTI128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPALIGNR128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPALIGNR256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPALIGNRMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPALIGNRMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPALIGNR,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPCLMULQDQ128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCLMULQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPCLMULQDQ256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCLMULQDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPCMPBMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPBMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPQ512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUBMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUBMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUQ512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPUWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPUW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPCMPWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
			},
		},
	},
	{
		name:      "VPERM2F128256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERM2F128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPERM2I128256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPERM2I128,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPROLD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLD512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQ128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQ256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQ512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPROLQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORD512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQ128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQ256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQ512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPRORQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDD128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDD256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQ128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQ256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQ512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDW128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDW256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHLDWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHLDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDD128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDD256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQ128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQ256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQ512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDQMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDW128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDW256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHRDWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    4,
		symEffect: SymRead,
		asm:       x86.AVPSHRDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFD512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFHW128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFHW256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFHWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFHWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFLW128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFLW256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VPSHUFLWMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSHUFLWMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLD512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLDMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLDMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLDMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLQ512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLQMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLQMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLQMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLWMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSLLWMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAD512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRADMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRADMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRADMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQ128constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQ256constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQ512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAQMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAWMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRAWMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLD512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLDMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLDMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLDMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLQ512constload",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLQMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLQMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLQMasked512constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLWMasked128constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VPSRLWMasked256constload",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD128load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD256load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGD512load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ128load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ256load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPTERNLOGQ512load",
		auxType:      auxSymValAndOff,
		argLen:       4,
		resultInArg0: true,
		symEffect:    SymRead,
		asm:          x86.AVPTERNLOGQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPD512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPS128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPS256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPS512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPSMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPSMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VREDUCEPSMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPD512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPDMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPDMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPDMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPS128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPS256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPS512load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPSMasked128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPSMasked256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VRNDSCALEPSMasked512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VROUNDPD128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVROUNDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VROUNDPD256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVROUNDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VROUNDPS128load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVROUNDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VROUNDPS256load",
		auxType:   auxSymValAndOff,
		argLen:    2,
		symEffect: SymRead,
		asm:       x86.AVROUNDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSHUFPD128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSHUFPD256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSHUFPD512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:      "VSHUFPS128load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSHUFPS256load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2147418112, v2: 0}},        // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 2147418112, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
			},
		},
	},
	{
		name:      "VSHUFPS512load",
		auxType:   auxSymValAndOff,
		argLen:    3,
		symEffect: SymRead,
		asm:       x86.AVSHUFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 72057594037977087, v2: 0}}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
				{0, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VADDPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVADDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VBROADCASTSDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VBROADCASTSDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVBROADCASTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VBROADCASTSSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VBROADCASTSSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VBROADCASTSSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVBROADCASTSS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTDQ2PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTDQ2PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTDQ2PSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTDQ2PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTDQ2PSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTPD2PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTPD2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTPD2PSXMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTPD2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTPD2PSYMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTPD2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTPS2PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTPS2PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTPS2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PSXMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTQQ2PSYMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2DQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2DQXMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2DQX,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2DQYMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2DQY,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2QQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2QQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2QQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UDQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UDQXMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UDQX,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UDQYMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UDQY,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UQQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UQQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPD2UQQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPD2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2DQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2DQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2DQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2DQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2QQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2QQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2QQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2UDQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2UDQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2UDQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2UDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2UQQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTTPS2UQQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTTPS2UQQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUDQ2PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUDQ2PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUDQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUDQ2PSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUDQ2PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUDQ2PSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUDQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PSXMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PSX,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VCVTUQQ2PSYMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVCVTUQQ2PSY,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VDIVPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVDIVPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VGF2P8MULBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VGF2P8MULBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VGF2P8MULBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVGF2P8MULB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMAXPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMAXPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMINPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMINPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VMULPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVMULPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSBMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSBMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSWMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPABSWMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPABSW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKSSDWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKSSDWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKSSDWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKSSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKUSDWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKUSDWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPACKUSDWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPACKUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDUSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPADDWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPANDQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPANDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPAVGWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPAVGW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTBMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTBMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTWMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPBROADCASTWMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPBROADCASTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPLZCNTQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPLZCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDUBSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDUBSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDUBSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDWDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDWDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMADDWDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMADDWD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMAXUWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMAXUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMINUWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMINUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVDWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQDMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQDMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVQWMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSDWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQDMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQDMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSQWMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSWBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSWBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSWBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBWMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXBWMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXDQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXDQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXDQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVSXWQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVSXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSDWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQBMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQDMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQDMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQWMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQWMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSQWMasked128_512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSQW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSWBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSWBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVUSWBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVUSWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVWBMasked128_128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVWBMasked128_256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVWBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVWB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBWMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXBWMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXBW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXDQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXDQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXDQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXDQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMOVZXWQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPMOVZXWQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHUWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHUWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHUWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHUW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULHWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPMULLWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTBMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTBMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTBMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTQMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTQMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTQMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTWMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTWMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPOPCNTWMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPORQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLVQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPROLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORVQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPRORVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSHUFB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLVWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSLLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAVWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRAVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLVWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSRLVW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSBMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSBMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSBMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSB,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBUSWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBWMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBWMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSUBWMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORQMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORQMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPXORQMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVPXORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRCP14PSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRCP14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRSQRT14PSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRSQRT14PS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSCALEFPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSCALEFPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPDMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPDMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPDMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPSMasked128Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPSMasked256Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSQRTPSMasked512Merging",
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVSQRTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPDMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPDMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPDMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPD,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPSMasked128Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPSMasked256Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VSUBPSMasked512Merging",
		argLen:       4,
		resultInArg0: true,
		asm:          x86.AVSUBPS,
		reg: regInfo{
			inputs: []inputInfo{
				{3, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{2, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLDMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLDMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLDMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLQMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLQMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPROLQMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPROLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORDMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORDMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORDMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORQMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORQMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPRORQMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPRORQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFDMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFDMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFDMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFHWMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFHWMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFHWMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFHW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFLWMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFLWMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSHUFLWMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSHUFLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLDMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLDMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLDMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLQMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLQMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLQMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLWMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLWMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSLLWMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRADMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRADMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRADMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAQMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAQMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAQMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAWMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAWMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRAWMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLDMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLDMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLDMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLQMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLQMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLQMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLQ,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLWMasked128constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLWMasked256constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VPSRLWMasked512constMerging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVPSRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPDMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPDMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPDMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPSMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPSMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VREDUCEPSMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVREDUCEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPDMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPDMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPDMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPD,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPSMasked128Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPSMasked256Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},
	{
		name:         "VRNDSCALEPSMasked512Merging",
		auxType:      auxUInt8,
		argLen:       3,
		resultInArg0: true,
		asm:          x86.AVRNDSCALEPS,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 71494644084506624, v2: 0}}, // K1 K2 K3 K4 K5 K6 K7
				{0, regMask{v1: 281472829161472, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
				{1, regMask{v1: 281474976645120, v2: 0}},   // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281472829161472, v2: 0}}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
			},
		},
	},

	{
		name:        "ADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 30719, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUB",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSB",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "MUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "HMUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "HMULU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMULLU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "CALLudiv",
		argLen:       2,
		clobberFlags: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}}, // R1
				{1, regMask{v1: 1, v2: 0}}, // R0
			},
			clobbers: regMask{v1: 20492, v2: 0}, // R2 R3 R12 R14
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // R0
				{1, regMask{v1: 2, v2: 0}}, // R1
			},
		},
	},
	{
		name:        "ADDS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDSconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "ADC",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCconst",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "ADCS",
		argLen:      3,
		commutative: true,
		asm:         arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "SUBS",
		argLen: 2,
		asm:    arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBSconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBSconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "SBC",
		argLen: 3,
		asm:    arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCconst",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCconst",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "MULLU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMULLU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MULA",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AMULA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MULS",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "ADDF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "ADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "SUBF",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "SUBD",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "MULF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMULF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "MULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "NMULF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.ANMULF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "NMULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.ANMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "DIVF",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ADIVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "DIVD",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "MULAF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMULAF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "MULAD",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMULAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "MULSF",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMULSF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "MULSD",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMULSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMULAD",
		argLen:       3,
		resultInArg0: true,
		asm:          arm.AFMULAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BIC",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BFX",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ABFX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BFXU",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ABFXU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVN",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "NEGF",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ANEGF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "NEGD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ANEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "SQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "SQRTF",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASQRTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "ABSD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "CLZ",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ACLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "REV",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AREV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "REV16",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AREV16,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RBIT",
		argLen:  1,
		earlyOk: true,
		asm:     arm.ARBIT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SLL",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SLLconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRL",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRLconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRA",
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRAconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRR",
		argLen:  2,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRRconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftRR",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftLL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftRL",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftRA",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftLL",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftRL",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftRA",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftLL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftRL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftRA",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftLL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftRL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftRA",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftLL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftRL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftRA",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDSshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDSshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDSshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBSshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBSshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBSshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBSshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBSshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBSshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADDshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SUBshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSBshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ANDshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ORshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "XORshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftLLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftRLreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "BICshiftRAreg",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftLLreg",
		argLen:  2,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftRLreg",
		argLen:  2,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MVNshiftRAreg",
		argLen:  2,
		earlyOk: true,
		asm:     arm.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftLLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftRLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "ADCshiftRAreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.AADC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftLLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftRLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SBCshiftRAreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ASBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftLLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftRLreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "RSCshiftRAreg",
		argLen:  4,
		earlyOk: true,
		asm:     arm.ARSC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "ADDSshiftLLreg",
		argLen: 3,
		asm:    arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "ADDSshiftRLreg",
		argLen: 3,
		asm:    arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "ADDSshiftRAreg",
		argLen: 3,
		asm:    arm.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "SUBSshiftLLreg",
		argLen: 3,
		asm:    arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "SUBSshiftRLreg",
		argLen: 3,
		asm:    arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "SUBSshiftRAreg",
		argLen: 3,
		asm:    arm.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "RSBSshiftLLreg",
		argLen: 3,
		asm:    arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "RSBSshiftRLreg",
		argLen: 3,
		asm:    arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "RSBSshiftRAreg",
		argLen: 3,
		asm:    arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMP",
		argLen: 2,
		asm:    arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMPconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:        "CMN",
		argLen:      2,
		commutative: true,
		asm:         arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMNconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:        "TST",
		argLen:      2,
		commutative: true,
		asm:         arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TSTconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:        "TEQ",
		argLen:      2,
		commutative: true,
		asm:         arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TEQconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:   "CMPF",
		argLen: 2,
		asm:    arm.ACMPF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:   "CMPD",
		argLen: 2,
		asm:    arm.ACMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "CMPshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMPshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMPshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMNshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMNshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "CMNshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TSTshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TSTshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TSTshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TEQshiftLL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TEQshiftRL",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "TEQshiftRA",
		auxType: auxInt32,
		argLen:  2,
		asm:     arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{1, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:   "CMPshiftLLreg",
		argLen: 3,
		asm:    arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMPshiftRLreg",
		argLen: 3,
		asm:    arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMPshiftRAreg",
		argLen: 3,
		asm:    arm.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMNshiftLLreg",
		argLen: 3,
		asm:    arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMNshiftRLreg",
		argLen: 3,
		asm:    arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMNshiftRAreg",
		argLen: 3,
		asm:    arm.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TSTshiftLLreg",
		argLen: 3,
		asm:    arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TSTshiftRLreg",
		argLen: 3,
		asm:    arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TSTshiftRAreg",
		argLen: 3,
		asm:    arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TEQshiftLLreg",
		argLen: 3,
		asm:    arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TEQshiftRLreg",
		argLen: 3,
		asm:    arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "TEQshiftRAreg",
		argLen: 3,
		asm:    arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "CMPF0",
		argLen: 1,
		asm:    arm.ACMPF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:   "CMPD0",
		argLen: 1,
		asm:    arm.ACMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "MOVWconst",
		auxType:           auxInt32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm.AMOVW,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:              "MOVFconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm.AMOVF,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "MOVWaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294975488, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "MOVFload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:           "MOVFstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "MOVWloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVWloadshiftLL",
		auxType:      auxInt32,
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVWloadshiftRL",
		auxType:      auxInt32,
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVWloadshiftRA",
		auxType:      auxInt32,
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVBUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVBloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVHUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVHloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVWstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:         "MOVWstoreshiftLL",
		auxType:      auxInt32,
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:         "MOVWstoreshiftRL",
		auxType:      auxInt32,
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:         "MOVWstoreshiftRA",
		auxType:      auxInt32,
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:         "MOVBstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:         "MOVHstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{2, regMask{v1: 22527, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
				{0, regMask{v1: 4294998015, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVHS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MOVWnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVWF",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVWF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "MOVWD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "MOVWUF",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVWF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "MOVWUD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "MOVFW",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVDW",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVFWU",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVDWU",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // F15
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "MOVFD",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "MOVDF",
		argLen:  1,
		earlyOk: true,
		asm:     arm.AMOVDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CMOVWHSconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "CMOVWLSconst",
		auxType:      auxInt32,
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "SRAcond",
		argLen:  3,
		earlyOk: true,
		asm:     arm.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       3,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 128, v2: 0}},   // R7
				{0, regMask{v1: 29695, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
			},
			clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 4294924287, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 22527, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:    "Equal",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "NotEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LessThan",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LessEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "GreaterThan",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "GreaterEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LessThanU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LessEqualU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "GreaterThanU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "GreaterEqualU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:           "DUFFZERO",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}}, // R1
				{1, regMask{v1: 1, v2: 0}}, // R0
			},
			clobbers: regMask{v1: 20482, v2: 0}, // R1 R12 R14
		},
	},
	{
		name:           "DUFFCOPY",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}}, // R2
				{1, regMask{v1: 2, v2: 0}}, // R1
			},
			clobbers: regMask{v1: 20487, v2: 0}, // R0 R1 R2 R12 R14
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},     // R1
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}},     // R2
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 6, v2: 0}, // R1 R2
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 128, v2: 0}}, // R7
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
				{1, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 5119, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:    "LoweredPanicExtendRR",
		auxType: auxInt64,
		argLen:  4,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 15, v2: 0}},    // R0 R1 R2 R3
				{1, regMask{v1: 15, v2: 0}},    // R0 R1 R2 R3
				{2, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:    "LoweredPanicExtendRC",
		auxType: auxPanicBoundsC,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3
				{1, regMask{v1: 15, v2: 0}}, // R0 R1 R2 R3
			},
		},
	},
	{
		name:    "FlagConstant",
		auxType: auxFlagConstant,
		argLen:  0,
		reg:     regInfo{},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 4294922240, v2: 0}, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			outputs: []outputInfo{
				{0, regMask{v1: 256, v2: 0}}, // R8
			},
		},
	},

	{
		name:        "ADCSflags",
		argLen:      3,
		commutative: true,
		asm:         arm64.AADCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADCzerocarry",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AADC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "ADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1476395007, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADDSconstflags",
		auxType: auxInt64,
		argLen:  1,
		asm:     arm64.AADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "ADDSflags",
		argLen:      2,
		commutative: true,
		asm:         arm64.AADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SUB",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SUBconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "SBCSflags",
		argLen: 3,
		asm:    arm64.ASBCS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "SUBSflags",
		argLen: 2,
		asm:    arm64.ASUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MULW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AMULW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MNEG",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AMNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MNEGW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AMNEGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MULH",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.ASMULH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "UMULH",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AUMULH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "MULL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.ASMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "UMULL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AUMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "DIV",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UDIV",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AUDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "DIVW",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASDIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UDIVW",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AUDIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOD",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AREM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UMOD",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AUREM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MODW",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AREMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UMODW",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AUREMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "FADDS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSUBS",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSUBD",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMULS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMULS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFNMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AFNMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FDIVS",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFDIVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FDIVD",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFDIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ANDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "BIC",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EON",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEON,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORN",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MVN",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NEG",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "NEGSflags",
		argLen: 1,
		asm:    arm64.ANEGS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NGCzerocarry",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ANGC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FABSD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FABSS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFABSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNEGS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFNEGS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNEGD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFNEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFSQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSQRTS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFSQRTS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMIND",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFMIND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMINS",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFMINS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMAXD",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFMAXD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMAXS",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AFMAXS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "REV",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AREV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "REVW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AREVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "REV16",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AREV16,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "REV16W",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AREV16W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "RBIT",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ARBIT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "RBITW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ARBITW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CLZ",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ACLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CLZW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ACLZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "VCNT",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AVCNT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUADDLV",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AVUADDLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMADDS",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMADDD",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNMADDS",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFNMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNMADDD",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFNMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMSUBS",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMSUBD",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNMSUBS",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFNMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNMSUBD",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AFNMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MADD",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AMADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MADDW",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AMADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MSUB",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AMSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MSUBW",
		argLen:  3,
		earlyOk: true,
		asm:     arm64.AMSUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{2, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SLL",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ALSL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SLLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ALSL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SRL",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ALSR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SRLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ALSR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SRA",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AASR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SRAconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AASR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ROR",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AROR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "RORW",
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ARORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "RORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AROR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "RORWconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ARORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EXTRconst",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEXTR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EXTRWconst",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEXTRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:   "CMP",
		argLen: 2,
		asm:    arm64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMPconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     arm64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    arm64.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMPWconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm64.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:        "CMN",
		argLen:      2,
		commutative: true,
		asm:         arm64.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMNconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     arm64.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:        "CMNW",
		argLen:      2,
		commutative: true,
		asm:         arm64.ACMNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMNWconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm64.ACMNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:        "TST",
		argLen:      2,
		commutative: true,
		asm:         arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:        "TSTW",
		argLen:      2,
		commutative: true,
		asm:         arm64.ATSTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTWconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     arm64.ATSTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:   "FCMPS",
		argLen: 2,
		asm:    arm64.AFCMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCMPD",
		argLen: 2,
		asm:    arm64.AFCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCMPS0",
		argLen: 1,
		asm:    arm64.AFCMPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCMPD0",
		argLen: 1,
		asm:    arm64.AFCMPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MVNshiftLL",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MVNshiftRL",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MVNshiftRA",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MVNshiftRO",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMVN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NEGshiftLL",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NEGshiftRL",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NEGshiftRA",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADDshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADDshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ADDshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SUBshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SUBshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SUBshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ANDshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ANDshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ANDshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ANDshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "XORshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "XORshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "XORshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "XORshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "BICshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "BICshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "BICshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "BICshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ABIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EONshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEON,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EONshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEON,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EONshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEON,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "EONshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AEON,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORNshiftLL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORNshiftRL",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORNshiftRA",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "ORNshiftRO",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CMPshiftLL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMPshiftRL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMPshiftRA",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMNshiftLL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMNshiftRL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CMNshiftRA",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ACMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTshiftLL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTshiftRL",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTshiftRA",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "TSTshiftRO",
		auxType: auxInt64,
		argLen:  2,
		asm:     arm64.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:         "BFI",
		auxType:      auxARM64BitField,
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm64.ABFI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "BFXIL",
		auxType:      auxARM64BitField,
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          arm64.ABFXIL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SBFIZ",
		auxType: auxARM64BitField,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASBFIZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SBFX",
		auxType: auxARM64BitField,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASBFX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UBFIZ",
		auxType: auxARM64BitField,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUBFIZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "UBFX",
		auxType: auxARM64BitField,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUBFX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm64.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:              "FMOVSconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm64.AFMOVS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "FMOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               arm64.AFMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVDaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037928517632, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVWUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "FMOVSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVQload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "LDP",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.ALDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:           "LDPW",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.ALDPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:           "LDPSW",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.ALDPSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:           "FLDPD",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFLDPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FLDPS",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFLDPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FLDPQ",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            arm64.AFLDPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVDloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVWloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVWUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVHloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVHUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVBloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVBUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "FMOVSloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "FMOVDloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVHloadidx2",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVHUloadidx2",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVWloadidx4",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVWUloadidx4",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVDloadidx8",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "FMOVSloadidx4",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "FMOVDloadidx8",
		argLen:       3,
		addrSinkArg0: true,
		asm:          arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "FMOVSstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVQstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFMOVQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "STP",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.ASTP,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "STPW",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.ASTPW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "FSTPD",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFSTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FSTPS",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFSTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FSTPQ",
		auxType:        auxSymOff,
		argLen:         4,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            arm64.AFSTPQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVBstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "MOVHstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "MOVWstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "MOVDstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "FMOVSstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "FMOVDstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVHstoreidx2",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "MOVWstoreidx4",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "MOVDstoreidx8",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:         "FMOVSstoreidx4",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "FMOVDstoreidx8",
		argLen:       4,
		addrSinkArg0: true,
		asm:          arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 402653183, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMOVDgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMOVDfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FMOVSgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMOVSfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVWUreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "MOVDreg",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "MOVDnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "SCVTFWS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASCVTFWS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SCVTFWD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASCVTFWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "UCVTFWS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUCVTFWS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "UCVTFWD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUCVTFWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SCVTFS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASCVTFS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SCVTFD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ASCVTFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "UCVTFS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUCVTFS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "UCVTFD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AUCVTFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTZSSW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZSSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZSDW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZSDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZUSW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZUSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZUDW",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZUDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZSS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZSD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZUS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZUS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTZUD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTZUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FCVTSD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTDS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFCVTDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTAD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTMD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTMD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTND",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTPD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTZD",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTZD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTAS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTAS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTMS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTMS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTNS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTNS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTPS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTPS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FRINTZS",
		argLen:  1,
		earlyOk: true,
		asm:     arm64.AFRINTZS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "CSEL",
		auxType: auxCCop,
		argLen:  3,
		earlyOk: true,
		asm:     arm64.ACSEL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CSEL0",
		auxType: auxCCop,
		argLen:  2,
		earlyOk: true,
		asm:     arm64.ACSEL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CSINC",
		auxType: auxCCop,
		argLen:  3,
		earlyOk: true,
		asm:     arm64.ACSINC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CSINV",
		auxType: auxCCop,
		argLen:  3,
		earlyOk: true,
		asm:     arm64.ACSINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CSNEG",
		auxType: auxCCop,
		argLen:  3,
		earlyOk: true,
		asm:     arm64.ACSNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{1, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CSETM",
		auxType: auxCCop,
		argLen:  1,
		earlyOk: true,
		asm:     arm64.ACSETM,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "CCMP",
		auxType: auxARM64ConditionalParams,
		argLen:  3,
		asm:     arm64.ACCMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMN",
		auxType: auxARM64ConditionalParams,
		argLen:  3,
		asm:     arm64.ACCMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMPconst",
		auxType: auxARM64ConditionalParams,
		argLen:  2,
		asm:     arm64.ACCMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMNconst",
		auxType: auxARM64ConditionalParams,
		argLen:  2,
		asm:     arm64.ACCMN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMPW",
		auxType: auxARM64ConditionalParams,
		argLen:  3,
		asm:     arm64.ACCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMNW",
		auxType: auxARM64ConditionalParams,
		argLen:  3,
		asm:     arm64.ACCMNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
				{1, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMPWconst",
		auxType: auxARM64ConditionalParams,
		argLen:  2,
		asm:     arm64.ACCMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:    "CCMNWconst",
		auxType: auxARM64ConditionalParams,
		argLen:  2,
		asm:     arm64.ACCMNW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 33554432, v2: 0}},   // R26
				{0, regMask{v1: 1409286143, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
			},
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 402653183, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
			},
		},
	},
	{
		name:           "LoweredMemEq",
		argLen:         4,
		clobberFlags:   true,
		call:           true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1, v2: 0}}, // R0
				{1, regMask{v1: 2, v2: 0}}, // R1
				{2, regMask{v1: 4, v2: 0}}, // R2
			},
			clobbers: regMask{v1: 9223372035109945343, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // R0
			},
		},
	},
	{
		name:    "Equal",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NotEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessThan",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterThan",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterEqual",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessThanU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessEqualU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterThanU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterEqualU",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessThanF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessEqualF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterThanF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterEqualF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NotLessThanF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NotLessEqualF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NotGreaterThanF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "NotGreaterEqualF",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "LessThanNoov",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "GreaterEqualNoov",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "LoweredZeroLoop",
		auxType:        auxInt64,
		argLen:         2,
		needIntTemp:    true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
			clobbersArg0: true,
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 318767103, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
				{1, regMask{v1: 318767103, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30
			},
			clobbers: regMask{v1: 422212481843200, v2: 0}, // R25 F16 F17
		},
	},
	{
		name:           "LoweredMoveLoop",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 310378495, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30
				{1, regMask{v1: 310378495, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R26 R30
			},
			clobbers:     regMask{v1: 422212490231808, v2: 0}, // R24 R25 F16 F17
			clobbersArg0: true,
			clobbersArg1: true,
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 33554432, v2: 0}}, // R26
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:    "FlagConstant",
		auxType: auxFlagConstant,
		argLen:  0,
		reg:     regInfo{},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:           "LDAR",
		argLen:         2,
		faultOnNilArg0: true,
		asm:            arm64.ALDAR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "LDARB",
		argLen:         2,
		faultOnNilArg0: true,
		asm:            arm64.ALDARB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "LDARW",
		argLen:         2,
		faultOnNilArg0: true,
		asm:            arm64.ALDARW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:           "STLRB",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            arm64.ASTLRB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "STLR",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            arm64.ASTLR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "STLRW",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            arm64.ASTLRW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange8",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange8Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicCas64",
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicCas32",
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicCas64Variant",
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicCas32Variant",
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{2, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd8",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr8",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd64",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr64",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd32",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr32",
		argLen:          3,
		resultNotInArgs: true,
		needIntTemp:     true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		asm:             arm64.AORR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd8Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr8Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd64Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr64Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicAnd32Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:            "LoweredAtomicOr32Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 939524095, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372034975924224, v2: 0}, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			outputs: []outputInfo{
				{0, regMask{v1: 16777216, v2: 0}}, // R25
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
				{1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:           "PRFM",
		auxType:        auxInt64,
		argLen:         2,
		hasSideEffects: true,
		asm:            arm64.APRFM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372038331170815, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
			},
		},
	},
	{
		name:           "DMB",
		auxType:        auxInt64,
		argLen:         1,
		hasSideEffects: true,
		asm:            arm64.ADMB,
		reg:            regInfo{},
	},
	{
		name:      "ZERO",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		earlyOk:   true,
		reg:       regInfo{},
	},
	{
		name:    "VMOVI16B",
		auxType: auxUInt8,
		argLen:  0,
		asm:     arm64.AVMOVI,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VABS2D",
		argLen: 1,
		asm:    arm64.AVABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VABS4S",
		argLen: 1,
		asm:    arm64.AVABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VABS8H",
		argLen: 1,
		asm:    arm64.AVABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VABS16B",
		argLen: 1,
		asm:    arm64.AVABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VADD2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VADD8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VADD16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDP2D",
		argLen: 2,
		asm:    arm64.AVADDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDP4S",
		argLen: 2,
		asm:    arm64.AVADDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDP8H",
		argLen: 2,
		asm:    arm64.AVADDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDV4S",
		argLen: 1,
		asm:    arm64.AVADDV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDV8H",
		argLen: 1,
		asm:    arm64.AVADDV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VADDV16B",
		argLen: 1,
		asm:    arm64.AVADDV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VAND16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VBIC16B",
		argLen: 2,
		asm:    arm64.AVBIC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VBIF16B",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVBIF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VBIT16B",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVBIT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLS4S",
		argLen: 1,
		asm:    arm64.AVCLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLS8H",
		argLen: 1,
		asm:    arm64.AVCLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLS16B",
		argLen: 1,
		asm:    arm64.AVCLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLZ4S",
		argLen: 1,
		asm:    arm64.AVCLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLZ8H",
		argLen: 1,
		asm:    arm64.AVCLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCLZ16B",
		argLen: 1,
		asm:    arm64.AVCLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VCMEQ2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VCMEQ4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VCMEQ8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VCMEQ16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGE2D",
		argLen: 2,
		asm:    arm64.AVCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGE4S",
		argLen: 2,
		asm:    arm64.AVCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGE8H",
		argLen: 2,
		asm:    arm64.AVCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGE16B",
		argLen: 2,
		asm:    arm64.AVCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGT2D",
		argLen: 2,
		asm:    arm64.AVCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGT4S",
		argLen: 2,
		asm:    arm64.AVCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGT8H",
		argLen: 2,
		asm:    arm64.AVCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMGT16B",
		argLen: 2,
		asm:    arm64.AVCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHI2D",
		argLen: 2,
		asm:    arm64.AVCMHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHI4S",
		argLen: 2,
		asm:    arm64.AVCMHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHI8H",
		argLen: 2,
		asm:    arm64.AVCMHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHI16B",
		argLen: 2,
		asm:    arm64.AVCMHI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHS2D",
		argLen: 2,
		asm:    arm64.AVCMHS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHS4S",
		argLen: 2,
		asm:    arm64.AVCMHS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHS8H",
		argLen: 2,
		asm:    arm64.AVCMHS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCMHS16B",
		argLen: 2,
		asm:    arm64.AVCMHS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VCNT16B",
		argLen: 1,
		asm:    arm64.AVCNT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VEOR16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVEOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFABS2D",
		argLen: 1,
		asm:    arm64.AVFABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFABS4S",
		argLen: 1,
		asm:    arm64.AVFABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFADD2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFADDP2D",
		argLen: 2,
		asm:    arm64.AVFADDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFADDP4S",
		argLen: 2,
		asm:    arm64.AVFADDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFCMEQ2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFCMEQ4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFCMEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCMGE2D",
		argLen: 2,
		asm:    arm64.AVFCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCMGE4S",
		argLen: 2,
		asm:    arm64.AVFCMGE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCMGT2D",
		argLen: 2,
		asm:    arm64.AVFCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCMGT4S",
		argLen: 2,
		asm:    arm64.AVFCMGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTL2_4S",
		argLen: 1,
		asm:    arm64.AVFCVTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTL4S",
		argLen: 1,
		asm:    arm64.AVFCVTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTN2D",
		argLen: 1,
		asm:    arm64.AVFCVTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VFCVTN2_2D",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVFCVTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTZS2D",
		argLen: 1,
		asm:    arm64.AVFCVTZS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTZS4S",
		argLen: 1,
		asm:    arm64.AVFCVTZS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTZU2D",
		argLen: 1,
		asm:    arm64.AVFCVTZU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFCVTZU4S",
		argLen: 1,
		asm:    arm64.AVFCVTZU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFDIV2D",
		argLen: 2,
		asm:    arm64.AVFDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFDIV4S",
		argLen: 2,
		asm:    arm64.AVFDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMAX2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMAX4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFMAXV4S",
		argLen: 1,
		asm:    arm64.AVFMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMIN2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMIN4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFMINV4S",
		argLen: 1,
		asm:    arm64.AVFMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VFMLA2D",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVFMLA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VFMLA4S",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVFMLA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMUL2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VFMUL4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVFMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFNEG2D",
		argLen: 1,
		asm:    arm64.AVFNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFNEG4S",
		argLen: 1,
		asm:    arm64.AVFNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTM2D",
		argLen: 1,
		asm:    arm64.AVFRINTM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTM4S",
		argLen: 1,
		asm:    arm64.AVFRINTM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTN2D",
		argLen: 1,
		asm:    arm64.AVFRINTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTN4S",
		argLen: 1,
		asm:    arm64.AVFRINTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTP2D",
		argLen: 1,
		asm:    arm64.AVFRINTP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTP4S",
		argLen: 1,
		asm:    arm64.AVFRINTP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTZ2D",
		argLen: 1,
		asm:    arm64.AVFRINTZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFRINTZ4S",
		argLen: 1,
		asm:    arm64.AVFRINTZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFSQRT2D",
		argLen: 1,
		asm:    arm64.AVFSQRT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFSQRT4S",
		argLen: 1,
		asm:    arm64.AVFSQRT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFSUB2D",
		argLen: 2,
		asm:    arm64.AVFSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VFSUB4S",
		argLen: 2,
		asm:    arm64.AVFSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VMLA4S",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVMLA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VMLA8H",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVMLA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VMLA16B",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVMLA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VMUL4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VMUL8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VMUL16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VNEG2D",
		argLen: 1,
		asm:    arm64.AVNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VNEG4S",
		argLen: 1,
		asm:    arm64.AVNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VNEG8H",
		argLen: 1,
		asm:    arm64.AVNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VNEG16B",
		argLen: 1,
		asm:    arm64.AVNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VNOT16B",
		argLen: 1,
		asm:    arm64.AVNOT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VORN16B",
		argLen: 2,
		asm:    arm64.AVORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VORR16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVORR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VPMULL2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVPMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VPMULL2_2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVPMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSCVTF2D",
		argLen: 1,
		asm:    arm64.AVSCVTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSCVTF4S",
		argLen: 1,
		asm:    arm64.AVSCVTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMAX4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMAX8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMAX16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMAXV4S",
		argLen: 1,
		asm:    arm64.AVSMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMAXV8H",
		argLen: 1,
		asm:    arm64.AVSMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMAXV16B",
		argLen: 1,
		asm:    arm64.AVSMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMIN4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMIN8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMIN16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMINV4S",
		argLen: 1,
		asm:    arm64.AVSMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMINV8H",
		argLen: 1,
		asm:    arm64.AVSMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSMINV16B",
		argLen: 1,
		asm:    arm64.AVSMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL2_4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL2_8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL2_16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSMULL16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSQADD2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSQADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSQADD8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSQADD16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSHL2D",
		argLen: 2,
		asm:    arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSHL4S",
		argLen: 2,
		asm:    arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSHL8H",
		argLen: 2,
		asm:    arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSHL16B",
		argLen: 2,
		asm:    arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSUB2D",
		argLen: 2,
		asm:    arm64.AVSQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSUB4S",
		argLen: 2,
		asm:    arm64.AVSQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSUB8H",
		argLen: 2,
		asm:    arm64.AVSQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQSUB16B",
		argLen: 2,
		asm:    arm64.AVSQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTN2D",
		argLen: 1,
		asm:    arm64.AVSQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTN2_2D",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTN2_4S",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTN2_8H",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTN4S",
		argLen: 1,
		asm:    arm64.AVSQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTN8H",
		argLen: 1,
		asm:    arm64.AVSQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTUN2D",
		argLen: 1,
		asm:    arm64.AVSQXTUN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTUN2_2D",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTUN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTUN2_4S",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTUN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSQXTUN2_8H",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSQXTUN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTUN4S",
		argLen: 1,
		asm:    arm64.AVSQXTUN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSQXTUN8H",
		argLen: 1,
		asm:    arm64.AVSQXTUN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSRHADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSRHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSRHADD8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSRHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VSRHADD16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVSRHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSSHL2D",
		argLen: 2,
		asm:    arm64.AVSSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSSHL4S",
		argLen: 2,
		asm:    arm64.AVSSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSSHL8H",
		argLen: 2,
		asm:    arm64.AVSSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSSHL16B",
		argLen: 2,
		asm:    arm64.AVSSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSUB2D",
		argLen: 2,
		asm:    arm64.AVSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSUB4S",
		argLen: 2,
		asm:    arm64.AVSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSUB8H",
		argLen: 2,
		asm:    arm64.AVSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSUB16B",
		argLen: 2,
		asm:    arm64.AVSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL2_4S",
		argLen: 1,
		asm:    arm64.AVSXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL2_8H",
		argLen: 1,
		asm:    arm64.AVSXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL2_16B",
		argLen: 1,
		asm:    arm64.AVSXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL4S",
		argLen: 1,
		asm:    arm64.AVSXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL8H",
		argLen: 1,
		asm:    arm64.AVSXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VSXTL16B",
		argLen: 1,
		asm:    arm64.AVSXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTBL16B",
		argLen: 2,
		asm:    arm64.AVTBL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VTBX16B",
		argLen:       3,
		resultInArg0: true,
		asm:          arm64.AVTBX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN12D",
		argLen: 2,
		asm:    arm64.AVTRN1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN14S",
		argLen: 2,
		asm:    arm64.AVTRN1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN18H",
		argLen: 2,
		asm:    arm64.AVTRN1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN22D",
		argLen: 2,
		asm:    arm64.AVTRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN24S",
		argLen: 2,
		asm:    arm64.AVTRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN28H",
		argLen: 2,
		asm:    arm64.AVTRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN116B",
		argLen: 2,
		asm:    arm64.AVTRN1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VTRN216B",
		argLen: 2,
		asm:    arm64.AVTRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUCVTF2D",
		argLen: 1,
		asm:    arm64.AVUCVTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUCVTF4S",
		argLen: 1,
		asm:    arm64.AVUCVTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMAX4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMAX8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMAX16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMAXV4S",
		argLen: 1,
		asm:    arm64.AVUMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMAXV8H",
		argLen: 1,
		asm:    arm64.AVUMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMAXV16B",
		argLen: 1,
		asm:    arm64.AVUMAXV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMIN4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMIN8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMIN16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMINV4S",
		argLen: 1,
		asm:    arm64.AVUMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMINV8H",
		argLen: 1,
		asm:    arm64.AVUMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUMINV16B",
		argLen: 1,
		asm:    arm64.AVUMINV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL2_4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL2_8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL2_16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUMULL16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUMULL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUQADD2D",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUQADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUQADD8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VUQADD16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVUQADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSHL2D",
		argLen: 2,
		asm:    arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSHL4S",
		argLen: 2,
		asm:    arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSHL8H",
		argLen: 2,
		asm:    arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSHL16B",
		argLen: 2,
		asm:    arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSUB2D",
		argLen: 2,
		asm:    arm64.AVUQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSUB4S",
		argLen: 2,
		asm:    arm64.AVUQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSUB8H",
		argLen: 2,
		asm:    arm64.AVUQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQSUB16B",
		argLen: 2,
		asm:    arm64.AVUQSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQXTN2D",
		argLen: 1,
		asm:    arm64.AVUQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VUQXTN2_2D",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVUQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VUQXTN2_4S",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVUQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VUQXTN2_8H",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVUQXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQXTN4S",
		argLen: 1,
		asm:    arm64.AVUQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUQXTN8H",
		argLen: 1,
		asm:    arm64.AVUQXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VURHADD4S",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVURHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VURHADD8H",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVURHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "VURHADD16B",
		argLen:      2,
		commutative: true,
		asm:         arm64.AVURHADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUSHL2D",
		argLen: 2,
		asm:    arm64.AVUSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUSHL4S",
		argLen: 2,
		asm:    arm64.AVUSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUSHL8H",
		argLen: 2,
		asm:    arm64.AVUSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUSHL16B",
		argLen: 2,
		asm:    arm64.AVUSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL2_4S",
		argLen: 1,
		asm:    arm64.AVUXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL2_8H",
		argLen: 1,
		asm:    arm64.AVUXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL2_16B",
		argLen: 1,
		asm:    arm64.AVUXTL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL4S",
		argLen: 1,
		asm:    arm64.AVUXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL8H",
		argLen: 1,
		asm:    arm64.AVUXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUXTL16B",
		argLen: 1,
		asm:    arm64.AVUXTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP12D",
		argLen: 2,
		asm:    arm64.AVUZP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP14S",
		argLen: 2,
		asm:    arm64.AVUZP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP18H",
		argLen: 2,
		asm:    arm64.AVUZP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP22D",
		argLen: 2,
		asm:    arm64.AVUZP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP24S",
		argLen: 2,
		asm:    arm64.AVUZP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP28H",
		argLen: 2,
		asm:    arm64.AVUZP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP116B",
		argLen: 2,
		asm:    arm64.AVUZP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VUZP216B",
		argLen: 2,
		asm:    arm64.AVUZP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VXTN2D",
		argLen: 1,
		asm:    arm64.AVXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VXTN2_2D",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VXTN2_4S",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VXTN2_8H",
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVXTN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VXTN4S",
		argLen: 1,
		asm:    arm64.AVXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VXTN8H",
		argLen: 1,
		asm:    arm64.AVXTN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP12D",
		argLen: 2,
		asm:    arm64.AVZIP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP14S",
		argLen: 2,
		asm:    arm64.AVZIP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP18H",
		argLen: 2,
		asm:    arm64.AVZIP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP22D",
		argLen: 2,
		asm:    arm64.AVZIP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP24S",
		argLen: 2,
		asm:    arm64.AVZIP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP28H",
		argLen: 2,
		asm:    arm64.AVZIP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP116B",
		argLen: 2,
		asm:    arm64.AVZIP1,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VZIP216B",
		argLen: 2,
		asm:    arm64.AVZIP2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPBbcast",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPDbcast",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPDextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPHbcast",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPSbcast",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VDUPSextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVDUP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VEXT16B",
		auxType: auxUInt8,
		argLen:  2,
		asm:     arm64.AVEXT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VMOVBextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "VMOVBins",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 335544319, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VMOVDextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "VMOVDins",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 335544319, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VMOVDins0",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VMOVHextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "VMOVHins",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 335544319, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VMOVSextr",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
			},
		},
	},
	{
		name:         "VMOVSins",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 335544319, v2: 0}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VMOVSins0",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHL2D",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHL4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHL8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHL16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHRN2D",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHRN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSHRN2_2D",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSHRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSHRN2_4S",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSHRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "VSHRN2_8H",
		auxType:      auxUInt8,
		argLen:       2,
		resultInArg0: true,
		asm:          arm64.AVSHRN2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHRN4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHRN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSHRN8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSHRN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSQSHL2Dconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSQSHL4Sconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSQSHL8Hconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSQSHL16Bconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL2_4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL2_8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL2_16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHLL16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHR2D",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHR4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHR8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VSSHR16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVSSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUQSHL2Dconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUQSHL4Sconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUQSHL8Hconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUQSHL16Bconst",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUQSHL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL2_4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL2_8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL2_16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHLL16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHR2D",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHR4S",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHR8H",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "VUSHR16B",
		auxType: auxUInt8,
		argLen:  1,
		asm:     arm64.AVUSHR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},

	{
		name:    "NEGV",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "NEGF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ANEGF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "NEGD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ANEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SQRTF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASQRTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "ABSF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AABSF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "ABSD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "CLZW",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ACLZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "CLZV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ACLZV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "CTZW",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ACTZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "CTZV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ACTZV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "REVB2H",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AREVB2H,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "REVB2W",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AREVB2W,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "REVB4H",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AREVB4H,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "REVBV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AREVBV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "BITREV4B",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ABITREV4B,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "BITREVW",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ABITREVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "BITREVV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ABITREVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "VPCNT64",
		argLen: 1,
		asm:    loong64.AVPCNTV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VPCNT32",
		argLen: 1,
		asm:    loong64.AVPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "VPCNT16",
		argLen: 1,
		asm:    loong64.AVPCNTH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "ADDV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AADDVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ADDVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AADDVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ADDV16const",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AADDV16,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SUBV",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASUBVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SUBVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASUBVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULHV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULHV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULHVU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULHVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULH",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULHU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "DIVV",
		argLen: 2,
		asm:    loong64.ADIVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "DIVVU",
		argLen: 2,
		asm:    loong64.ADIVVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "REMV",
		argLen: 2,
		asm:    loong64.AREMV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "REMVU",
		argLen: 2,
		asm:    loong64.AREMVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULWVW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULWVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "MULWVWU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULWVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "ADDF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "ADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SUBF",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SUBD",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "MULF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "MULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "DIVF",
		argLen: 2,
		asm:    loong64.ADIVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "DIVD",
		argLen: 2,
		asm:    loong64.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ANDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "NOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.ANOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "NORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ANOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ANDN",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ORN",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:        "FMADDF",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFMADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMADDD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMSUBF",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFMSUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMSUBD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMADDF",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFNMADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMADDD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFNMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMSUBF",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFNMSUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMSUBD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         loong64.AFNMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "FMINF",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             loong64.AFMINF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "FMIND",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             loong64.AFMIND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "FMAXF",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             loong64.AFMAXF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "FMAXD",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             loong64.AFMAXD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MASKEQZ",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AMASKEQZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MASKNEZ",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AMASKNEZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "FCOPYSGD",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AFCOPYSGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SLL",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SLLV",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASLLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SLLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SLLVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASLLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRL",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRLV",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASRLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRLVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASRLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRA",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRAV",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASRAV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRAconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SRAVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASRAV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ROTR",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AROTR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ROTRV",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AROTRV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ROTRconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AROTR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ROTRVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AROTRV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SGT",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SGTconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SGTU",
		argLen:  2,
		earlyOk: true,
		asm:     loong64.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "SGTUconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:   "CMPEQF",
		argLen: 2,
		asm:    loong64.ACMPEQF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPEQD",
		argLen: 2,
		asm:    loong64.ACMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGEF",
		argLen: 2,
		asm:    loong64.ACMPGEF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGED",
		argLen: 2,
		asm:    loong64.ACMPGED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGTF",
		argLen: 2,
		asm:    loong64.ACMPGTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGTD",
		argLen: 2,
		asm:    loong64.ACMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "BSTRPICKW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ABSTRPICKW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "BSTRPICKV",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ABSTRPICKV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:              "MOVVconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               loong64.AMOVV,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:              "MOVFconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               loong64.AMOVF,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               loong64.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVVaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018427387908, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVWUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVVload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "MOVFload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            loong64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVVloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVWloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVWUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVHloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVHUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVBloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVBUloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVFloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVDloadidx",
		argLen:       3,
		addrSinkArg0: true,
		asm:          loong64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "MOVVstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "MOVFstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            loong64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
				{1, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVBstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:         "MOVHstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:         "MOVWstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:         "MOVVstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741817, v2: 0}},          // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:         "MOVFstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "MOVDstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		asm:          loong64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
				{2, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVWfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVWgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVVgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVWUreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVVreg",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "MOVVnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "MOVWF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVWF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVWD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCFW",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ATRUNCFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCDW",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ATRUNCDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCFV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ATRUNCFV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCDV",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.ATRUNCDV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVFD",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVDF",
		argLen:  1,
		earlyOk: true,
		asm:     loong64.AMOVDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FRINTND",
		argLen: 1,
		asm:    loong64.AVFRINTRNED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FRINTMD",
		argLen: 1,
		asm:    loong64.AVFRINTRMD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FRINTPD",
		argLen: 1,
		asm:    loong64.AVFRINTRPD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FRINTZD",
		argLen: 1,
		asm:    loong64.AVFRINTRZD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4611686017353646080, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 268435456, v2: 0}},  // R29
				{0, regMask{v1: 1071644668, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			clobbers: regMask{v1: 4611686018427387896, v2: 0}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "LoweredZeroLoop",
		auxType:        auxInt64,
		argLen:         2,
		needIntTemp:    true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
			clobbers:     regMask{v1: 2305843009213693952, v2: 0}, // F31
			clobbersArg0: true,
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1067450360, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1067450360, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 R29 R31
			},
			clobbers: regMask{v1: 4194304, v2: 0}, // R23
		},
	},
	{
		name:           "LoweredMoveLoop",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1059061752, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1059061752, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R25 R26 R27 R28 R29 R31
			},
			clobbers:     regMask{v1: 12582912, v2: 0}, // R23 R24
			clobbersArg0: true,
			clobbersArg1: true,
		},
	},
	{
		name:           "LoweredAtomicLoad8",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "LoweredAtomicLoad32",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "LoweredAtomicLoad64",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "LoweredAtomicStore8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore64",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore8Variant",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore32Variant",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore64Variant",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicExchange8Variant",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas32",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas64",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas64Variant",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas32Variant",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{2, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAnd32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMANDDBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:            "LoweredAtomicOr32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMORDBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
		},
	},
	{
		name:            "LoweredAtomicAnd32value",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMANDDBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAnd64value",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMANDDBV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicOr32value",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMORDBW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:            "LoweredAtomicOr64value",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		asm:             loong64.AAMORDBV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741816, v2: 0}},          // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{0, regMask{v1: 4611686019501129724, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "FPFlagTrue",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "FPFlagFalse",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 268435456, v2: 0}}, // R29
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686017353646082, v2: 0}, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			outputs: []outputInfo{
				{0, regMask{v1: 268435456, v2: 0}}, // R29
			},
		},
	},
	{
		name:           "LoweredPubBarrier",
		argLen:         1,
		hasSideEffects: true,
		asm:            loong64.ADBAR,
		reg:            regInfo{},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
				{1, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 524280, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:           "PRELD",
		auxType:        auxInt64,
		argLen:         2,
		hasSideEffects: true,
		asm:            loong64.APRELD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:           "PRELDX",
		auxType:        auxInt64,
		argLen:         2,
		hasSideEffects: true,
		asm:            loong64.APRELDX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741820, v2: 0}}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:    "ADDshiftLLV",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     loong64.AALSLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073741816, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
				{1, regMask{v1: 1073741817, v2: 0}}, // ZERO R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1071644664, v2: 0}}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
			},
		},
	},
	{
		name:      "ZERO",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		earlyOk:   true,
		reg:       regInfo{},
	},

	{
		name:        "ADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "ADDconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AADDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 536870910, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SUB",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SUBconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASUBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "MUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "MULT",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "MULTU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:   "DIV",
		argLen: 2,
		asm:    mips.ADIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:   "DIVU",
		argLen: 2,
		asm:    mips.ADIVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			clobbers: regMask{v1: 105553116266496, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "ADDF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:        "ADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "SUBF",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "SUBD",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:        "MULF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:        "MULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "DIVF",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ADIVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "DIVD",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "ANDconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:        "NOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.ANOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "NEG",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "NEGF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ANEGF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "NEGD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ANEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "ABSD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "SQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "SQRTF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASQRTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "SLL",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SLLconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SRL",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SRLconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SRA",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SRAconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "CLZ",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ACLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGT",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGTconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGTzero",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGTU",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGTUconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "SGTUzero",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:   "CMPEQF",
		argLen: 2,
		asm:    mips.ACMPEQF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:   "CMPEQD",
		argLen: 2,
		asm:    mips.ACMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:   "CMPGEF",
		argLen: 2,
		asm:    mips.ACMPGEF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:   "CMPGED",
		argLen: 2,
		asm:    mips.ACMPGED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:   "CMPGTF",
		argLen: 2,
		asm:    mips.ACMPGTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:   "CMPGTD",
		argLen: 2,
		asm:    mips.ACMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{1, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:              "MOVWconst",
		auxType:           auxInt32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVW,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:              "MOVFconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVF,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:              "MOVWaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140737555464192, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "MOVFload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVFstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 35183835217920, v2: 0}},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 35183835217920, v2: 0}},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVBstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVHstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVWstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:    "MOVWfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVWgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:         "MOVWnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:         "CMOVZ",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          mips.ACMOVZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{2, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:         "CMOVZzero",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          mips.ACMOVZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
				{1, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "MOVWF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVWF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "MOVWD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "TRUNCFW",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "TRUNCDW",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "MOVFD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:    "MOVDF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 35183835217920, v2: 0}}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       3,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4194304, v2: 0}},   // R22
				{0, regMask{v1: 402653182, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
			},
			clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			clobbers: regMask{v1: 140737421246462, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
		},
	},
	{
		name:           "LoweredAtomicLoad8",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "LoweredAtomicLoad32",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "LoweredAtomicStore8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStorezero",
		argLen:         2,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:            "LoweredAtomicExchange",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAdd",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAddconst",
		auxType:         auxInt32,
		argLen:          2,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{2, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "LoweredAtomicAnd",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		unsafePoint:    true,
		asm:            mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicOr",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		unsafePoint:    true,
		asm:            mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 469762046, v2: 0}},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
				{0, regMask{v1: 140738025226238, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt32,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},         // R1
				{1, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt32,
		argLen:         4,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}},         // R2
				{1, regMask{v1: 2, v2: 0}},         // R1
				{2, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
			clobbers: regMask{v1: 6, v2: 0}, // R1 R2
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 469762046, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
			},
		},
	},
	{
		name:    "FPFlagTrue",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:    "FPFlagFalse",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4194304, v2: 0}}, // R22
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 335544318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 140737219919872, v2: 0}, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 16777216, v2: 0}}, // R25
			},
		},
	},
	{
		name:           "LoweredPubBarrier",
		argLen:         1,
		hasSideEffects: true,
		asm:            mips.ASYNC,
		reg:            regInfo{},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
				{1, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:    "LoweredPanicExtendRR",
		auxType: auxInt64,
		argLen:  4,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 30, v2: 0}},     // R1 R2 R3 R4
				{1, regMask{v1: 30, v2: 0}},     // R1 R2 R3 R4
				{2, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicExtendRC",
		auxType: auxPanicBoundsC,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4
				{1, regMask{v1: 30, v2: 0}}, // R1 R2 R3 R4
			},
		},
	},

	{
		name:        "ADDV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "ADDVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AADDVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 268435454, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SUBV",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SUBVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASUBVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "MULV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
				{1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "MULVU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
				{1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:   "DIVV",
		argLen: 2,
		asm:    mips.ADIVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
				{1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:   "DIVVU",
		argLen: 2,
		asm:    mips.ADIVVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			clobbers: regMask{v1: 3458764513820540928, v2: 0}, // HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
				{1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "ADDF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "ADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SUBF",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SUBD",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "MULF",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "MULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "DIVF",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ADIVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "DIVD",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "ANDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:        "NOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         mips.ANOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "NEGV",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "NEGF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ANEGF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "NEGD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ANEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "ABSF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AABSF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "ABSD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SQRTF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASQRTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "SLLV",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASLLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SLLVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASLLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SRLV",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASRLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SRLVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASRLV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SRAV",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASRAV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SRAVconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASRAV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SGT",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SGTconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SGTU",
		argLen:  2,
		earlyOk: true,
		asm:     mips.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{1, regMask{v1: 234881023, v2: 0}}, // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "SGTUconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     mips.ASGTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:   "CMPEQF",
		argLen: 2,
		asm:    mips.ACMPEQF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPEQD",
		argLen: 2,
		asm:    mips.ACMPEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGEF",
		argLen: 2,
		asm:    mips.ACMPGEF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGED",
		argLen: 2,
		asm:    mips.ACMPGED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGTF",
		argLen: 2,
		asm:    mips.ACMPGTF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "CMPGTD",
		argLen: 2,
		asm:    mips.ACMPGTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVVconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVV,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:              "MOVFconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVF,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               mips.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "MOVVaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018460942336, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVWUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVVload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "MOVFload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            mips.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVVstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "MOVFstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            mips.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
				{1, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:      "ZERO",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		earlyOk:   true,
		reg:       regInfo{},
	},
	{
		name:    "MOVWfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVWgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVfpgp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVVgpfp",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVWUreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVVreg",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:         "MOVVnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "MOVWF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVWF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVWD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVVD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCFW",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCFW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCDW",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCFV",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCFV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "TRUNCDV",
		argLen:  1,
		earlyOk: true,
		asm:     mips.ATRUNCDV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVFD",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVFD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "MOVDF",
		argLen:  1,
		earlyOk: true,
		asm:     mips.AMOVDF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1152921504338411520, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       3,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4194304, v2: 0}},   // R22
				{0, regMask{v1: 201326590, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
			},
			clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       2,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			clobbers: regMask{v1: 4611686018393833470, v2: 0}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
		},
	},
	{
		name:           "DUFFZERO",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			clobbers: regMask{v1: 134217730, v2: 0}, // R1 R31
		},
	},
	{
		name:           "DUFFCOPY",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}}, // R2
				{1, regMask{v1: 2, v2: 0}}, // R1
			},
			clobbers: regMask{v1: 134217734, v2: 0}, // R1 R2 R31
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},         // R1
				{1, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4, v2: 0}},         // R2
				{1, regMask{v1: 2, v2: 0}},         // R1
				{2, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
			clobbers: regMask{v1: 6, v2: 0}, // R1 R2
		},
	},
	{
		name:           "LoweredAtomicAnd32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		unsafePoint:    true,
		asm:            mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicOr32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		unsafePoint:    true,
		asm:            mips.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicLoad8",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "LoweredAtomicLoad32",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "LoweredAtomicLoad64",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "LoweredAtomicStore8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore64",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881023, v2: 0}},           // ZERO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStorezero32",
		argLen:         2,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStorezero64",
		argLen:         2,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAddconst32",
		auxType:         auxInt32,
		argLen:          2,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicAddconst64",
		auxType:         auxInt64,
		argLen:          2,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas32",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{2, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:            "LoweredAtomicCas64",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{2, regMask{v1: 234881022, v2: 0}},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
				{0, regMask{v1: 4611686018695823358, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 234881022, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
			},
		},
	},
	{
		name:    "FPFlagTrue",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:    "FPFlagFalse",
		argLen:  1,
		earlyOk: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4194304, v2: 0}}, // R22
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 167772158, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 4611686018293170176, v2: 0}, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
			outputs: []outputInfo{
				{0, regMask{v1: 16777216, v2: 0}}, // R25
			},
		},
	},
	{
		name:           "LoweredPubBarrier",
		argLen:         1,
		hasSideEffects: true,
		asm:            mips.ASYNC,
		reg:            regInfo{},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
				{1, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 131070, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},

	{
		name:        "ADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ADDCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AADDCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ADDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ADDCCconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.AADDCCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "FADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AFADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:        "FADDS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AFADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "SUB",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "SUBCC",
		argLen: 2,
		asm:    ppc64.ASUBCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SUBFCconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ASUBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "FSUB",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AFSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FSUBS",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AFSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "XSMINJDP",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AXSMINJDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "XSMAXJDP",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AXSMAXJDP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:        "MULLD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULLW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MULLDconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MULLWconst",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MADDLD",
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AMADDLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULHD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULHD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULHW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULHW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULHDU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULHDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULHDUCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AMULHDUCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "MULHWU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AMULHWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "FMUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AFMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:        "FMULS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AFMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FMADD",
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AFMADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FMADDS",
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AFMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FMSUB",
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AFMSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FMSUBS",
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AFMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "SRAD",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRAW",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRD",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRW",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SLD",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SLW",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ASLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ROTL",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AROTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ROTLW",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AROTLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CLRLSLWI",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACLRLSLWI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CLRLSLDI",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACLRLSLDI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ADDC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AADDC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "SUBC",
		argLen: 2,
		asm:    ppc64.ASUBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ADDCconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.AADDC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SUBCconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ASUBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ADDE",
		argLen:      3,
		commutative: true,
		asm:         ppc64.AADDE,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "ADDZE",
		argLen: 2,
		asm:    ppc64.AADDZE,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "SUBE",
		argLen: 3,
		asm:    ppc64.ASUBE,
		reg: regInfo{
			inputs: []inputInfo{
				{2, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{1, regMask{v1: 9223372036854775808, v2: 0}}, // XER
				{0, regMask{v1: 1073733624, v2: 0}},          // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ADDZEzero",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AADDZE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372036854775808, v2: 0}}, // XER
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SUBZEzero",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASUBZE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372036854775808, v2: 0}}, // XER
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRADconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRAWconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 9223372036854775808, v2: 0}, // XER
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SRWconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SLDconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SLWconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ROTLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AROTL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ROTLWconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AROTLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "EXTSWSLconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AEXTSWSLI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLWINM",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ARLWNM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLWNM",
		auxType: auxInt64,
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.ARLWNM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "RLWMI",
		auxType:      auxInt64,
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          ppc64.ARLWMI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLDICL",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ARLDICL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLDICLCC",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ARLDICLCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "RLDICR",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ARLDICR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CNTLZD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACNTLZD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "CNTLZDCC",
		argLen: 1,
		asm:    ppc64.ACNTLZDCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CNTLZW",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACNTLZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CNTTZD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACNTTZD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CNTTZW",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ACNTTZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "POPCNTD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.APOPCNTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "POPCNTW",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.APOPCNTW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "POPCNTB",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.APOPCNTB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "FDIV",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AFDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FDIVS",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AFDIVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:   "DIVD",
		argLen: 2,
		asm:    ppc64.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "DIVW",
		argLen: 2,
		asm:    ppc64.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "DIVDU",
		argLen: 2,
		asm:    ppc64.ADIVDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "DIVWU",
		argLen: 2,
		asm:    ppc64.ADIVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "MODUD",
		argLen: 2,
		asm:    ppc64.AMODUD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "MODSD",
		argLen: 2,
		asm:    ppc64.AMODSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "MODUW",
		argLen: 2,
		asm:    ppc64.AMODUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "MODSW",
		argLen: 2,
		asm:    ppc64.AMODSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "FCTIDZ",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFCTIDZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FCTIWZ",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFCTIWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FCFID",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFCFID,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FCFIDS",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFCFIDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FRSP",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFRSP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "MFVSRD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMFVSRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MTVSRD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMTVSRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ANDN",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "ANDNCC",
		argLen: 2,
		asm:    ppc64.AANDNCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ANDCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AANDCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ORN",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "ORCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AORCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "NOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.ANOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "NORCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.ANORCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "XORCC",
		argLen:      2,
		commutative: true,
		asm:         ppc64.AXORCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:        "EQV",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         ppc64.AEQV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "NEG",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "NEGCC",
		argLen: 1,
		asm:    ppc64.ANEGCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "BRD",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ABRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "BRW",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ABRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "BRH",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ABRH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "FNEG",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FSQRT",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFSQRT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FSQRTS",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFSQRTS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FFLOOR",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFRIM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FCEIL",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFRIP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FTRUNC",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFRIZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FROUND",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFRIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FABS",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FNABS",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AFNABS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "FCPSGN",
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AFCPSGN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:    "ORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "XORconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ANDCCconst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AANDCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "ANDconst",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          ppc64.AANDCC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVBZreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVHZreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "MOVWZreg",
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVBZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVDBRload",
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWBRload",
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHBRload",
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVBZloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVHloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVHZloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVWloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVWZloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVDloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVHBRloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVWBRloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVDBRloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "FMOVDloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "FMOVSloadidx",
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:           "DCBT",
		auxType:        auxInt64,
		argLen:         2,
		hasSideEffects: true,
		asm:            ppc64.ADCBT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVDBRstore",
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWBRstore",
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHBRstore",
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		asm:            ppc64.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "FMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:           "FMOVSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            ppc64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "FMOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:           "FMOVSstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "MOVBstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVHstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVWstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVDstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "FMOVDstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "FMOVSstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}},          // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "MOVHBRstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVWBRstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "MOVDBRstoreidx",
		argLen:       4,
		addrSinkArg0: true,
		addrSinkArg1: true,
		asm:          ppc64.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVBstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVHstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVWstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "MOVDstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:              "MOVDaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               ppc64.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               ppc64.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:              "FMOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               ppc64.AFMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:              "FMOVSconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               ppc64.AFMOVS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:   "FCMPU",
		argLen: 2,
		asm:    ppc64.AFCMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
				{1, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:   "CMP",
		argLen: 2,
		asm:    ppc64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "CMPU",
		argLen: 2,
		asm:    ppc64.ACMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    ppc64.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "CMPWU",
		argLen: 2,
		asm:    ppc64.ACMPWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CMPconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CMPUconst",
		auxType: auxInt64,
		argLen:  1,
		asm:     ppc64.ACMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CMPWconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     ppc64.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "CMPWUconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     ppc64.ACMPWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ISEL",
		auxType: auxInt32,
		argLen:  3,
		earlyOk: true,
		asm:     ppc64.AISEL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "ISELZ",
		auxType: auxInt32,
		argLen:  2,
		earlyOk: true,
		asm:     ppc64.AISEL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SETBC",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASETBC,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:    "SETBCR",
		auxType: auxInt32,
		argLen:  1,
		earlyOk: true,
		asm:     ppc64.ASETBCR,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "Equal",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "NotEqual",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "LessThan",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "FLessThan",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "LessEqual",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "FLessEqual",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "GreaterThan",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "FGreaterThan",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "GreaterEqual",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:   "FGreaterEqual",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 2048, v2: 0}}, // R11
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		clobberFlags:   true,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			clobbers: regMask{v1: 2147483648, v2: 0}, // R31
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372032559808512, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4096, v2: 0}}, // R12
			},
			clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4096, v2: 0}}, // R12
				{1, regMask{v1: 2048, v2: 0}}, // R11
			},
			clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4096, v2: 0}}, // R12
			},
			clobbers: regMask{v1: 18446744071562059768, v2: 0}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048576, v2: 0}}, // R20
			},
			clobbers: regMask{v1: 1048576, v2: 0}, // R20
		},
	},
	{
		name:           "LoweredZeroShort",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredQuadZeroShort",
		auxType:        auxInt64,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredQuadZero",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048576, v2: 0}}, // R20
			},
			clobbers: regMask{v1: 1048576, v2: 0}, // R20
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048576, v2: 0}}, // R20
				{1, regMask{v1: 2097152, v2: 0}}, // R21
			},
			clobbers: regMask{v1: 3145728, v2: 0}, // R20 R21
		},
	},
	{
		name:           "LoweredMoveShort",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredQuadMove",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048576, v2: 0}}, // R20
				{1, regMask{v1: 2097152, v2: 0}}, // R21
			},
			clobbers: regMask{v1: 3145728, v2: 0}, // R20 R21
		},
	},
	{
		name:           "LoweredQuadMoveShort",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		unsafePoint:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicStore8",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicStore32",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicStore64",
		auxType:        auxInt64,
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicLoad8",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicLoad32",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicLoad64",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicLoadPtr",
		auxType:        auxInt64,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32",
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64",
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicExchange8",
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32",
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64",
		argLen:          3,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicCas64",
		auxType:         auxInt64,
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:            "LoweredAtomicCas32",
		auxType:         auxInt64,
		argLen:          4,
		resultNotInArgs: true,
		clobberFlags:    true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{2, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1073733624, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicAnd8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            ppc64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicAnd32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            ppc64.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicOr8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            ppc64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:           "LoweredAtomicOr32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            ppc64.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
				{1, regMask{v1: 1073733630, v2: 0}}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 18446744072632408064, v2: 0}, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER
			outputs: []outputInfo{
				{0, regMask{v1: 536870912, v2: 0}}, // R29
			},
		},
	},
	{
		name:           "LoweredPubBarrier",
		argLen:         1,
		hasSideEffects: true,
		asm:            ppc64.ALWSYNC,
		reg:            regInfo{},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9
				{1, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1016, v2: 0}}, // R3 R4 R5 R6 R7 R8 R9
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:   "FlagEQ",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT",
		argLen: 0,
		reg:    regInfo{},
	},

	{
		name:        "ADD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ADDI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AADDI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ADDIW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AADDIW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "NEG",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "NEGW",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ANEGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SUB",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SUBW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MUL",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MULW",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMULW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MULH",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMULH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MULHU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMULHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredMuluhilo",
		argLen:          2,
		resultNotInArgs: true,
		earlyOk:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredMuluover",
		argLen:          2,
		resultNotInArgs: true,
		earlyOk:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "DIV",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ADIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "DIVU",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ADIVU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "DIVW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "DIVUW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ADIVUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "REM",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AREM,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "REMU",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AREMU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "REMW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AREMW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "REMUW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AREMUW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:              "MOVaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		asm:               riscv.AMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               riscv.AMOV,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:              "FMOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               riscv.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:              "FMOVFconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               riscv.AMOVF,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVBUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVHUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVWUload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVBstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVHstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVWstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "MOVDstorezero",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVDreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVBUreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVBU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVHUreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVHU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "MOVWUreg",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AMOVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:         "MOVDnop",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLL",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLLW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASLLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRA",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRAW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRL",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASRL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRLW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASRLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLLI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASLLI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLLIW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASLLIW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRAI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASRAI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRAIW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASRAIW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRLI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASRLI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SRLIW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASRLIW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SH1ADD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASH1ADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SH2ADD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASH2ADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SH3ADD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASH3ADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "AND",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ANDN",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AANDN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ANDI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AANDI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "CLZ",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ACLZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "CLZW",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ACLZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "CPOP",
		argLen: 1,
		asm:    riscv.ACPOP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "CPOPW",
		argLen: 1,
		asm:    riscv.ACPOPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "CTZ",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ACTZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "CTZW",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ACTZW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "NOT",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ANOT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "OR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ORN",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AORN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ORI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AORI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "REV8",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AREV8,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ROL",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AROL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ROLW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AROLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "ROR",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AROR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "RORI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ARORI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "RORIW",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ARORIW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "RORW",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ARORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "XNOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AXNOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "XOR",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "XORI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AXORI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MIN",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMIN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MAX",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMAX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MINU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMINU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "MAXU",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AMAXU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SEQZ",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASEQZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SNEZ",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASNEZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLT",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASLT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLTI",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASLTI,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLTU",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.ASLTU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "SLTIU",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     riscv.ASLTIU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "CALLstatic",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:     "CALLtail",
		auxType:  auxCallOff,
		argLen:   -1,
		call:     true,
		tailCall: true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:     "CALLtailinter",
		auxType:  auxCallOff,
		argLen:   -1,
		call:     true,
		tailCall: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:    "CALLclosure",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 33554432, v2: 0}},   // X26
				{0, regMask{v1: 1006632930, v2: 0}}, // SP X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:    "CALLinter",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbers: regMask{v1: 9223372035781033968, v2: 0}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "LoweredZeroLoop",
		auxType:        auxSymValAndOff,
		argLen:         2,
		needIntTemp:    true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbersArg0: true,
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxSymValAndOff,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		symEffect:      SymWrite,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632928, v2: 0}}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbers: regMask{v1: 16, v2: 0}, // X5
		},
	},
	{
		name:           "LoweredMoveLoop",
		auxType:        auxSymValAndOff,
		argLen:         3,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		symEffect:      SymWrite,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632896, v2: 0}}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632896, v2: 0}}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			clobbers:     regMask{v1: 48, v2: 0}, // X5 X6
			clobbersArg0: true,
			clobbersArg1: true,
		},
	},
	{
		name:           "LoweredAtomicLoad8",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "LoweredAtomicLoad32",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "LoweredAtomicLoad64",
		argLen:         2,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "LoweredAtomicStore8",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:           "LoweredAtomicStore64",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1006632946, v2: 0}},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
		},
	},
	{
		name:            "LoweredAtomicExchange32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredAtomicExchange64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd32",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredAtomicAdd64",
		argLen:          3,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredAtomicCas32",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{2, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredAtomicCas64",
		argLen:          4,
		resultNotInArgs: true,
		faultOnNilArg0:  true,
		hasSideEffects:  true,
		unsafePoint:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{2, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "LoweredAtomicAnd32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            riscv.AAMOANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
		},
	},
	{
		name:           "LoweredAtomicOr32",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		asm:            riscv.AAMOORW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1073741808, v2: 0}},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
				{0, regMask{v1: 9223372037928517618, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632946, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "LoweredGetClosurePtr",
		argLen: 0,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 33554432, v2: 0}}, // X26
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 9223372034707292160, v2: 0}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			outputs: []outputInfo{
				{0, regMask{v1: 8388608, v2: 0}}, // X24
			},
		},
	},
	{
		name:           "LoweredPubBarrier",
		argLen:         1,
		hasSideEffects: true,
		asm:            riscv.AFENCE,
		reg:            regInfo{},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
				{1, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1048560, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:        "FADDS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSUBS",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMULS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FDIVS",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFDIVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMADDS",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMSUBS",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMADDS",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMSUBS",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSQRTS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFSQRTS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FABSS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFABSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNEGS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFNEGS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMVSX",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFMVSX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMVXS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFMVXS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCVTSW",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTSW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTSL",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTSL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTWS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTWS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCVTLS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTLS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:           "FMOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            riscv.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVF,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FEQS",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFEQS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "FNES",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNES,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FLTS",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFLTS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FLES",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFLES,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredFMAXS",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             riscv.AFMAXS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "LoweredFMINS",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             riscv.AFMINS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FADDD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSUBD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMULD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMULD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FDIVD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFDIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMADDD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FMSUBD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMADDD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNMADDD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FNMSUBD",
		argLen:      3,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNMSUBD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{2, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSQRTD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFSQRTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FNEGD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFNEGD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FABSD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFABSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FSGNJD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFSGNJD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMVDX",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFMVDX,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FMVXD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFMVXD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCVTDW",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTDL",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTDL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTWD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTWD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCVTLD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCVTDS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCVTSD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCVTSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            riscv.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:           "FMOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		symEffect:      SymWrite,
		asm:            riscv.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372037861408754, v2: 0}}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:        "FEQD",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFEQD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:        "FNED",
		argLen:      2,
		commutative: true,
		earlyOk:     true,
		asm:         riscv.AFNED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FLTD",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFLTD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FLED",
		argLen:  2,
		earlyOk: true,
		asm:     riscv.AFLED,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:            "LoweredFMIND",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             riscv.AFMIND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:            "LoweredFMAXD",
		argLen:          2,
		commutative:     true,
		resultNotInArgs: true,
		earlyOk:         true,
		asm:             riscv.AFMAXD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "FCLASSS",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCLASSS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:    "FCLASSD",
		argLen:  1,
		earlyOk: true,
		asm:     riscv.AFCLASSD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 9223372034707292160, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "CZEROEQZ",
		argLen: 2,
		asm:    riscv.ACZEROEQZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "CZERONEZ",
		argLen: 2,
		asm:    riscv.ACZERONEZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
				{1, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
			outputs: []outputInfo{
				{0, regMask{v1: 1006632944, v2: 0}}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},

	{
		name:         "FADDS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FADD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FSUBS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FSUB",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMULS",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMULS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMUL",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMUL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FDIVS",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFDIVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FDIV",
		argLen:       2,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFDIV,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FNEGS",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AFNEGS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FNEG",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AFNEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMADDS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMADDS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMADD",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMSUBS",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMSUBS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMSUB",
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.AFMSUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "LPDFR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALPDFR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "LNDFR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALNDFR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "CPSDR",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ACPSDR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "WFMAXDB",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.AWFMAXDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "WFMAXSB",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.AWFMAXSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "WFMINDB",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.AWFMINDB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "WFMINSB",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.AWFMINSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "FIDBR",
		auxType: auxInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AFIDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "FMOVSload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "FMOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "FMOVSconst",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               s390x.AFMOVS,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "FMOVDconst",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               s390x.AFMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMOVSloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          s390x.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMOVDloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		addrSinkArg0: true,
		symEffect:    SymRead,
		asm:          s390x.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "FMOVSstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:           "FMOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMOVSstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          s390x.AFMOVS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "FMOVDstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		addrSinkArg0: true,
		symEffect:    SymWrite,
		asm:          s390x.AFMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "ADD",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ADDW",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ADDconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ADDWconst",
		auxType:      auxInt32,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ADDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AADD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ADDWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AADDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SUB",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SUBW",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SUBconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SUBWconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "SUBload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.ASUB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "SUBWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.ASUBW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MULLD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MULLW",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MULLDconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MULLWconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MULLDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AMULLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MULLWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AMULLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MULHD",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULHD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MULHDU",
		argLen:       2,
		commutative:  true,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AMULHDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "DIVD",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.ADIVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "DIVW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.ADIVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "DIVDU",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.ADIVDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "DIVWU",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.ADIVWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MODD",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.AMODD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MODW",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.AMODW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MODDU",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.AMODDU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "MODWU",
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		asm:          s390x.AMODWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			clobbers: regMask{v1: 2048, v2: 0}, // R11
			outputs: []outputInfo{
				{0, regMask{v1: 21503, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:         "AND",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ANDW",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ANDconst",
		auxType:      auxInt64,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ANDWconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ANDload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AAND,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ANDWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AANDW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "OR",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ORW",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ORconst",
		auxType:      auxInt64,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ORWconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ORload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "ORWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "XOR",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "XORW",
		argLen:       2,
		commutative:  true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AXORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "XORconst",
		auxType:      auxInt64,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "XORWconst",
		auxType:      auxInt32,
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AXORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "XORload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AXOR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "XORWload",
		auxType:        auxSymOff,
		argLen:         3,
		resultInArg0:   true,
		clobberFlags:   true,
		faultOnNilArg1: true,
		addrSinkArg1:   true,
		symEffect:      SymRead,
		asm:            s390x.AXORW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:        "ADDC",
		argLen:      2,
		commutative: true,
		asm:         s390x.AADDC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "ADDCconst",
		auxType: auxInt16,
		argLen:  1,
		asm:     s390x.AADDC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "ADDE",
		argLen:       3,
		commutative:  true,
		resultInArg0: true,
		asm:          s390x.AADDE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:   "SUBC",
		argLen: 2,
		asm:    s390x.ASUBC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SUBE",
		argLen:       3,
		resultInArg0: true,
		asm:          s390x.ASUBE,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:   "CMP",
		argLen: 2,
		asm:    s390x.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:   "CMPW",
		argLen: 2,
		asm:    s390x.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:   "CMPU",
		argLen: 2,
		asm:    s390x.ACMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:   "CMPWU",
		argLen: 2,
		asm:    s390x.ACMPWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:    "CMPconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     s390x.ACMP,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:    "CMPWconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     s390x.ACMPW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:    "CMPUconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     s390x.ACMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:    "CMPWUconst",
		auxType: auxInt32,
		argLen:  1,
		asm:     s390x.ACMPWU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:   "FCMPS",
		argLen: 2,
		asm:    s390x.ACEBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:   "FCMP",
		argLen: 2,
		asm:    s390x.AFCMPU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:   "LTDBR",
		argLen: 1,
		asm:    s390x.ALTDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:   "LTEBR",
		argLen: 1,
		asm:    s390x.ALTEBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "SLD",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ASLD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SLW",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ASLW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SLDconst",
		auxType: auxUInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ASLD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SLWconst",
		auxType: auxUInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ASLW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SRD",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ASRD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SRW",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ASRW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SRDconst",
		auxType: auxUInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ASRD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "SRWconst",
		auxType: auxUInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ASRW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SRAD",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SRAW",
		argLen:       2,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SRADconst",
		auxType:      auxUInt8,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASRAD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "SRAWconst",
		auxType:      auxUInt8,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ASRAW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "RLLG",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ARLLG,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "RLL",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.ARLL,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "RLLconst",
		auxType: auxUInt8,
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ARLL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "RXSBG",
		auxType:      auxS390XRotateParams,
		argLen:       2,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ARXSBG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "RISBGZ",
		auxType:      auxS390XRotateParams,
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ARISBGZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "NEG",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ANEG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "NEGW",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ANEGW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "NOT",
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "NOTW",
		argLen:       1,
		resultInArg0: true,
		clobberFlags: true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "FSQRT",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AFSQRT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "FSQRTS",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AFSQRTS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "LOCGR",
		auxType:      auxS390XCCMask,
		argLen:       3,
		resultInArg0: true,
		earlyOk:      true,
		asm:          s390x.ALOCGR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
				{1, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVBreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVBZreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVHreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVHZreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVWreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVWZreg",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:              "MOVDconst",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		asm:               s390x.AMOVD,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "LDGR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALDGR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "LGDR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALGDR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CFDBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACFDBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CGDBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACGDBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CFEBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACFEBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CGEBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACGEBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CEFBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACEFBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CDFBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACDFBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CEGBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACEGBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CDGBRA",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACDGBRA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CLFEBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACLFEBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CLFDBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACLFDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CLGEBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACLGEBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CLGDBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACLGDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CELFBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACELFBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CDLFBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACDLFBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CELGBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACELGBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "CDLGBR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.ACDLGBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "LEDBR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALEDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "LDEBR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.ALDEBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "MOVDaddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295000064, v2: 0}}, // SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:      "MOVDaddridx",
		auxType:   auxSymOff,
		argLen:    2,
		earlyOk:   true,
		symEffect: SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295000064, v2: 0}}, // SP SB
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVBZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVBload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVHZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVHload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVWZload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVWload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVDload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVWBR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MOVDBR",
		argLen:  1,
		earlyOk: true,
		asm:     s390x.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVHBRload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVWBRload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVDBRload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymRead,
		asm:            s390x.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVBstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVHstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVWstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVDstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVHBRstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVWBRstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVDBRstore",
		auxType:        auxSymOff,
		argLen:         3,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MVC",
		auxType:        auxSymValAndOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		symEffect:      SymNone,
		asm:            s390x.AMVC,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVBZloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVBloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVHZloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVHZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVHloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVWZloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVWloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVDloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVHBRloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVWBRloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVDBRloadidx",
		auxType:      auxSymOff,
		argLen:       3,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymRead,
		asm:          s390x.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 56318, v2: 0}},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "MOVBstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVHstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVWstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVDstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVHBRstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVHBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVWBRstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVWBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "MOVDBRstoreidx",
		auxType:      auxSymOff,
		argLen:       4,
		commutative:  true,
		addrSinkArg0: true,
		addrSinkArg1: true,
		symEffect:    SymWrite,
		asm:          s390x.AMOVDBR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVBstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
		},
	},
	{
		name:           "MOVHstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVH,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
		},
	},
	{
		name:           "MOVWstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
		},
	},
	{
		name:           "MOVDstoreconst",
		auxType:        auxSymValAndOff,
		argLen:         2,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
		},
	},
	{
		name:           "CLEAR",
		auxType:        auxSymValAndOff,
		argLen:         2,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ACLEAR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:         "CALLstatic",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLtail",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLtailinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		tailCall:     true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLclosure",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4096, v2: 0}},  // R12
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:         "CALLinter",
		auxType:      auxCallOff,
		argLen:       -1,
		clobberFlags: true,
		call:         true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23550, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			clobbers: regMask{v1: 4294933503, v2: 0}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
		},
	},
	{
		name:   "InvertFlags",
		argLen: 1,
		reg:    regInfo{},
	},
	{
		name:   "LoweredGetG",
		argLen: 1,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:      "LoweredGetClosurePtr",
		argLen:    0,
		zeroWidth: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4096, v2: 0}}, // R12
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		clobberFlags:   true,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:         "LoweredRound32F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "LoweredRound64F",
		argLen:       1,
		resultInArg0: true,
		zeroWidth:    true,
		earlyOk:      true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "LoweredWB",
		auxType:      auxInt64,
		argLen:       1,
		clobberFlags: true,
		reg: regInfo{
			clobbers: regMask{v1: 4294918146, v2: 0}, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			outputs: []outputInfo{
				{0, regMask{v1: 512, v2: 0}}, // R9
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRR",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
				{1, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsRC",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCR",
		auxType: auxPanicBoundsC,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 7167, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12
			},
		},
	},
	{
		name:    "LoweredPanicBoundsCC",
		auxType: auxPanicBoundsCC,
		argLen:  1,
		call:    true,
		reg:     regInfo{},
	},
	{
		name:   "FlagEQ",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagLT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagGT",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "FlagOV",
		argLen: 0,
		reg:    regInfo{},
	},
	{
		name:   "SYNC",
		argLen: 1,
		asm:    s390x.ASYNC,
		reg:    regInfo{},
	},
	{
		name:           "MOVBZatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            s390x.AMOVBZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVWZatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            s390x.AMOVWZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVDatomicload",
		auxType:        auxSymOff,
		argLen:         2,
		faultOnNilArg0: true,
		symEffect:      SymRead,
		asm:            s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "MOVBatomicstore",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVWatomicstore",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVW,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "MOVDatomicstore",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymWrite,
		asm:            s390x.AMOVD,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "LAA",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ALAA,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "LAAG",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ALAAG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:   "AddTupleFirst32",
		argLen: 2,
		reg:    regInfo{},
	},
	{
		name:   "AddTupleFirst64",
		argLen: 2,
		reg:    regInfo{},
	},
	{
		name:           "LAN",
		argLen:         3,
		clobberFlags:   true,
		hasSideEffects: true,
		asm:            s390x.ALAN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "LANfloor",
		argLen:         3,
		clobberFlags:   true,
		hasSideEffects: true,
		asm:            s390x.ALAN,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},     // R1
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},
	{
		name:           "LAO",
		argLen:         3,
		clobberFlags:   true,
		hasSideEffects: true,
		asm:            s390x.ALAO,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4295023614, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
				{1, regMask{v1: 56319, v2: 0}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "LAOfloor",
		argLen:         3,
		clobberFlags:   true,
		hasSideEffects: true,
		asm:            s390x.ALAO,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},     // R1
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},
	{
		name:           "LoweredAtomicCas32",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ACS,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1, v2: 0}},     // R0
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 1, v2: 0}, // R0
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "LoweredAtomicCas64",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ACSG,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 1, v2: 0}},     // R0
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 1, v2: 0}, // R0
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:           "LoweredAtomicExchange32",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ACS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // R0
			},
		},
	},
	{
		name:           "LoweredAtomicExchange64",
		auxType:        auxSymOff,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		hasSideEffects: true,
		symEffect:      SymRdWr,
		asm:            s390x.ACSG,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
				{1, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			outputs: []outputInfo{
				{1, regMask{v1: 0, v2: 0}},
				{0, regMask{v1: 1, v2: 0}}, // R0
			},
		},
	},
	{
		name:         "FLOGR",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.AFLOGR,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
			outputs: []outputInfo{
				{0, regMask{v1: 1, v2: 0}}, // R0
			},
		},
	},
	{
		name:         "POPCNT",
		argLen:       1,
		clobberFlags: true,
		earlyOk:      true,
		asm:          s390x.APOPCNT,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
		},
	},
	{
		name:    "MLGR",
		argLen:  2,
		earlyOk: true,
		asm:     s390x.AMLGR,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 8, v2: 0}},     // R3
				{0, regMask{v1: 23551, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4, v2: 0}}, // R2
				{1, regMask{v1: 8, v2: 0}}, // R3
			},
		},
	},
	{
		name:    "SumBytes2",
		argLen:  1,
		earlyOk: true,
		reg:     regInfo{},
	},
	{
		name:    "SumBytes4",
		argLen:  1,
		earlyOk: true,
		reg:     regInfo{},
	},
	{
		name:    "SumBytes8",
		argLen:  1,
		earlyOk: true,
		reg:     regInfo{},
	},
	{
		name:           "STMG2",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMG,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "STMG3",
		auxType:        auxSymOff,
		argLen:         5,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMG,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{3, regMask{v1: 8, v2: 0}},     // R3
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "STMG4",
		auxType:        auxSymOff,
		argLen:         6,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMG,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{3, regMask{v1: 8, v2: 0}},     // R3
				{4, regMask{v1: 16, v2: 0}},    // R4
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "STM2",
		auxType:        auxSymOff,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "STM3",
		auxType:        auxSymOff,
		argLen:         5,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{3, regMask{v1: 8, v2: 0}},     // R3
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "STM4",
		auxType:        auxSymOff,
		argLen:         6,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		symEffect:      SymWrite,
		asm:            s390x.ASTMY,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 2, v2: 0}},     // R1
				{2, regMask{v1: 4, v2: 0}},     // R2
				{3, regMask{v1: 8, v2: 0}},     // R3
				{4, regMask{v1: 16, v2: 0}},    // R4
				{0, regMask{v1: 56318, v2: 0}}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
		},
	},
	{
		name:           "LoweredMove",
		auxType:        auxInt64,
		argLen:         4,
		clobberFlags:   true,
		faultOnNilArg0: true,
		faultOnNilArg1: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},     // R1
				{1, regMask{v1: 4, v2: 0}},     // R2
				{2, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 6, v2: 0}, // R1 R2
		},
	},
	{
		name:           "LoweredZero",
		auxType:        auxInt64,
		argLen:         3,
		clobberFlags:   true,
		faultOnNilArg0: true,
		addrSinkArg0:   true,
		addrSinkArg1:   true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 2, v2: 0}},     // R1
				{1, regMask{v1: 56319, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
			},
			clobbers: regMask{v1: 2, v2: 0}, // R1
		},
	},

	{
		name:    "LoweredStaticCall",
		auxType: auxCallOff,
		argLen:  1,
		call:    true,
		reg: regInfo{
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
		},
	},
	{
		name:     "LoweredTailCall",
		auxType:  auxCallOff,
		argLen:   1,
		call:     true,
		tailCall: true,
		reg: regInfo{
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
		},
	},
	{
		name:     "LoweredTailCallInter",
		auxType:  auxCallOff,
		argLen:   2,
		call:     true,
		tailCall: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
		},
	},
	{
		name:    "LoweredClosureCall",
		auxType: auxCallOff,
		argLen:  3,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
				{1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
		},
	},
	{
		name:    "LoweredInterCall",
		auxType: auxCallOff,
		argLen:  2,
		call:    true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
		},
	},
	{
		name:              "LoweredAddr",
		auxType:           auxSymOff,
		argLen:            1,
		rematerializeable: true,
		earlyOk:           true,
		symEffect:         SymAddr,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "LoweredMove",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		addrSinkArg1: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
				{1, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "LoweredZero",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "LoweredGetClosurePtr",
		argLen: 0,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:              "LoweredGetCallerPC",
		argLen:            0,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:              "LoweredGetCallerSP",
		argLen:            1,
		rematerializeable: true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:           "LoweredNilCheck",
		argLen:         2,
		nilCheck:       true,
		faultOnNilArg0: true,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "LoweredWB",
		auxType: auxInt64,
		argLen:  1,
		reg: regInfo{
			clobbers: regMask{v1: 18446744073709551615, v2: 2}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 g
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "LoweredConvert",
		argLen: 2,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "Select",
		argLen:  3,
		earlyOk: true,
		asm:     wasm.ASelect,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{2, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "SelectV",
		argLen:  3,
		earlyOk: true,
		asm:     wasm.ASelect,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{2, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:         "I64Load8U",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load8U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load8S",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load16U",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load16U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load16S",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load32U",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load32U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load32S",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load32S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Load",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AI64Load,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:         "I64Store8",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AI64Store8,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:         "I64Store16",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AI64Store16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:         "I64Store32",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AI64Store32,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:         "I64Store",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AI64Store,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:         "F32Load",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AF32Load,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:         "F64Load",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AF64Load,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "F32Store",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AF32Store,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{0, regMask{v1: 65535, v2: 5}},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:         "F64Store",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AF64Store,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{0, regMask{v1: 65535, v2: 5}},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:              "I64Const",
		auxType:           auxInt64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:              "F32Const",
		auxType:           auxFloat32,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:              "F64Const",
		auxType:           auxFloat64,
		argLen:            0,
		rematerializeable: true,
		earlyOk:           true,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:         "V128Load",
		auxType:      auxInt64,
		argLen:       2,
		addrSinkArg0: true,
		asm:          wasm.AV128Load,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 5}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:         "V128Store",
		auxType:      auxInt64,
		argLen:       3,
		addrSinkArg0: true,
		asm:          wasm.AV128Store,
		reg: regInfo{
			inputs: []inputInfo{
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{0, regMask{v1: 65535, v2: 5}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:   "V128Zero",
		argLen: 0,
		asm:    wasm.AV128Const,
		reg: regInfo{
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I64Eqz",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Eqz,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Eq",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Ne",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64LtS",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64LtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64LtU",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64LtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64GtS",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64GtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64GtU",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64GtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64LeS",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64LeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64LeU",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64LeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64GeS",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64GeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64GeU",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64GeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Eq",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Ne",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Lt",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Lt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Gt",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Gt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Le",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Le,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Ge",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Ge,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Eq",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Ne",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Lt",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Lt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Gt",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Gt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Le",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Le,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64Ge",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Ge,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Add",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64AddConst",
		auxType: auxInt64,
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Sub",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Mul",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64DivS",
		argLen: 2,
		asm:    wasm.AI64DivS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64DivU",
		argLen: 2,
		asm:    wasm.AI64DivU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64RemS",
		argLen: 2,
		asm:    wasm.AI64RemS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I64RemU",
		argLen: 2,
		asm:    wasm.AI64RemU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64And",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64And,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Or",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Or,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Xor",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Xor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Shl",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64ShrS",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64ShrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64ShrU",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64ShrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Neg",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Add",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Sub",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Mul",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Div",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Div,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F64Neg",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Add",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Sub",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Mul",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Div",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Div,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "I64TruncSatF64S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64TruncSatF64S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64TruncSatF64U",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64TruncSatF64U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64TruncSatF32S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64TruncSatF32S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64TruncSatF32U",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64TruncSatF32U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32ConvertI64S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32ConvertI64S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32ConvertI64U",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32ConvertI64U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F64ConvertI64S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64ConvertI64S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64ConvertI64U",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64ConvertI64U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F32DemoteF64",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32DemoteF64,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F64PromoteF32",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64PromoteF32,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "I64Extend8S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Extend8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Extend16S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Extend16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Extend32S",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Extend32S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32Sqrt",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Sqrt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Trunc",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Trunc,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Ceil",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Ceil,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Floor",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Floor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Nearest",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Nearest,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Abs",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF32Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F32Copysign",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF32Copysign,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
				{1, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "F64Sqrt",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Sqrt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Trunc",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Trunc,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Ceil",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Ceil,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Floor",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Floor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Nearest",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Nearest,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Abs",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AF64Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "F64Copysign",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AF64Copysign,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
				{1, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:    "I64Ctz",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Ctz,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Clz",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Clz,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I32Rotl",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI32Rotl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Rotl",
		argLen:  2,
		earlyOk: true,
		asm:     wasm.AI64Rotl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
				{1, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Popcnt",
		argLen:  1,
		earlyOk: true,
		asm:     wasm.AI64Popcnt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 1}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:   "I8x16AllTrue",
		argLen: 1,
		asm:    wasm.AI8x16AllTrue,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "V128AnyTrue",
		argLen: 1,
		asm:    wasm.AV128AnyTrue,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8AllTrue",
		argLen: 1,
		asm:    wasm.AI16x8AllTrue,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Q15MulrSatS",
		argLen: 2,
		asm:    wasm.AI16x8Q15MulrSatS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8RelaxedQ15MulrS",
		argLen: 2,
		asm:    wasm.AI16x8RelaxedQ15MulrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4AllTrue",
		argLen: 1,
		asm:    wasm.AI32x4AllTrue,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Pmax",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Pmax,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Pmin",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Pmin,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4RelaxedMax",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4RelaxedMax,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4RelaxedMin",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4RelaxedMin,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2AllTrue",
		argLen: 1,
		asm:    wasm.AI64x2AllTrue,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Pmax",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Pmax,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Pmin",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Pmin,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2RelaxedMax",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2RelaxedMax,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2RelaxedMin",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2RelaxedMin,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Abs",
		argLen: 1,
		asm:    wasm.AI8x16Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Abs",
		argLen: 1,
		asm:    wasm.AI16x8Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4Abs",
		argLen: 1,
		asm:    wasm.AI32x4Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Abs",
		argLen: 1,
		asm:    wasm.AF32x4Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2Abs",
		argLen: 1,
		asm:    wasm.AI64x2Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Abs",
		argLen: 1,
		asm:    wasm.AF64x2Abs,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Add",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Add,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16AddSatS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16AddSatS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16AddSatU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16AddSatU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8AddSatS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8AddSatS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8AddSatU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8AddSatU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "V128And",
		argLen:      2,
		commutative: true,
		asm:         wasm.AV128And,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "V128Andnot",
		argLen: 2,
		asm:    wasm.AV128Andnot,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16AvgrU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16AvgrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8AvgrU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8AvgrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "V128Bitselect",
		argLen: 3,
		asm:    wasm.AV128Bitselect,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{2, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Splat",
		argLen: 1,
		asm:    wasm.AI8x16Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Splat",
		argLen: 1,
		asm:    wasm.AI16x8Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4Splat",
		argLen: 1,
		asm:    wasm.AI32x4Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Splat",
		argLen: 1,
		asm:    wasm.AF32x4Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2Splat",
		argLen: 1,
		asm:    wasm.AI64x2Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Splat",
		argLen: 1,
		asm:    wasm.AF64x2Splat,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Ceil",
		argLen: 1,
		asm:    wasm.AF32x4Ceil,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Ceil",
		argLen: 1,
		asm:    wasm.AF64x2Ceil,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2ConvertLowI32x4S",
		argLen: 1,
		asm:    wasm.AF64x2ConvertLowI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2ConvertLowI32x4U",
		argLen: 1,
		asm:    wasm.AF64x2ConvertLowI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4ConvertI32x4S",
		argLen: 1,
		asm:    wasm.AF32x4ConvertI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4ConvertI32x4U",
		argLen: 1,
		asm:    wasm.AF32x4ConvertI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4TruncSatF32x4S",
		argLen: 1,
		asm:    wasm.AI32x4TruncSatF32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4TruncSatF32x4U",
		argLen: 1,
		asm:    wasm.AI32x4TruncSatF32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Div",
		argLen: 2,
		asm:    wasm.AF32x4Div,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Div",
		argLen: 2,
		asm:    wasm.AF64x2Div,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Eq",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Eq,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ExtendHighI32x4S",
		argLen: 1,
		asm:    wasm.AI64x2ExtendHighI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ExtendHighI32x4U",
		argLen: 1,
		asm:    wasm.AI64x2ExtendHighI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ExtendHighI16x8S",
		argLen: 1,
		asm:    wasm.AI32x4ExtendHighI16x8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ExtendHighI16x8U",
		argLen: 1,
		asm:    wasm.AI32x4ExtendHighI16x8U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ExtendHighI8x16S",
		argLen: 1,
		asm:    wasm.AI16x8ExtendHighI8x16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ExtendHighI8x16U",
		argLen: 1,
		asm:    wasm.AI16x8ExtendHighI8x16U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ExtendLowI32x4S",
		argLen: 1,
		asm:    wasm.AI64x2ExtendLowI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ExtendLowI32x4U",
		argLen: 1,
		asm:    wasm.AI64x2ExtendLowI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ExtendLowI16x8S",
		argLen: 1,
		asm:    wasm.AI32x4ExtendLowI16x8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ExtendLowI16x8U",
		argLen: 1,
		asm:    wasm.AI32x4ExtendLowI16x8U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ExtendLowI8x16S",
		argLen: 1,
		asm:    wasm.AI16x8ExtendLowI8x16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ExtendLowI8x16U",
		argLen: 1,
		asm:    wasm.AI16x8ExtendLowI8x16U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Floor",
		argLen: 1,
		asm:    wasm.AF32x4Floor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Floor",
		argLen: 1,
		asm:    wasm.AF64x2Floor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I8x16ExtractLaneS",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI8x16ExtractLaneS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I8x16ExtractLaneU",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI8x16ExtractLaneU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I16x8ExtractLaneS",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI16x8ExtractLaneS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I16x8ExtractLaneU",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI16x8ExtractLaneU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I32x4ExtractLane",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI32x4ExtractLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F32x4ExtractLane",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AF32x4ExtractLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 4294901760, v2: 0}}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
		},
	},
	{
		name:    "I64x2ExtractLane",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AI64x2ExtractLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 65535, v2: 0}}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "F64x2ExtractLane",
		auxType: auxUInt8,
		argLen:  1,
		asm:     wasm.AF64x2ExtractLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 281470681743360, v2: 0}}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "I8x16GtS",
		argLen: 2,
		asm:    wasm.AI8x16GtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16GtU",
		argLen: 2,
		asm:    wasm.AI8x16GtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8GtS",
		argLen: 2,
		asm:    wasm.AI16x8GtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8GtU",
		argLen: 2,
		asm:    wasm.AI16x8GtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4GtS",
		argLen: 2,
		asm:    wasm.AI32x4GtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4GtU",
		argLen: 2,
		asm:    wasm.AI32x4GtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Gt",
		argLen: 2,
		asm:    wasm.AF32x4Gt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2GtS",
		argLen: 2,
		asm:    wasm.AI64x2GtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Gt",
		argLen: 2,
		asm:    wasm.AF64x2Gt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16GeS",
		argLen: 2,
		asm:    wasm.AI8x16GeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16GeU",
		argLen: 2,
		asm:    wasm.AI8x16GeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8GeS",
		argLen: 2,
		asm:    wasm.AI16x8GeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8GeU",
		argLen: 2,
		asm:    wasm.AI16x8GeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4GeS",
		argLen: 2,
		asm:    wasm.AI32x4GeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4GeU",
		argLen: 2,
		asm:    wasm.AI32x4GeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Ge",
		argLen: 2,
		asm:    wasm.AF32x4Ge,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2GeS",
		argLen: 2,
		asm:    wasm.AI64x2GeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Ge",
		argLen: 2,
		asm:    wasm.AF64x2Ge,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16LtS",
		argLen: 2,
		asm:    wasm.AI8x16LtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16LtU",
		argLen: 2,
		asm:    wasm.AI8x16LtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8LtS",
		argLen: 2,
		asm:    wasm.AI16x8LtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8LtU",
		argLen: 2,
		asm:    wasm.AI16x8LtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4LtS",
		argLen: 2,
		asm:    wasm.AI32x4LtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4LtU",
		argLen: 2,
		asm:    wasm.AI32x4LtU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Lt",
		argLen: 2,
		asm:    wasm.AF32x4Lt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2LtS",
		argLen: 2,
		asm:    wasm.AI64x2LtS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Lt",
		argLen: 2,
		asm:    wasm.AF64x2Lt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16LeS",
		argLen: 2,
		asm:    wasm.AI8x16LeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16LeU",
		argLen: 2,
		asm:    wasm.AI8x16LeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8LeS",
		argLen: 2,
		asm:    wasm.AI16x8LeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8LeU",
		argLen: 2,
		asm:    wasm.AI16x8LeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4LeS",
		argLen: 2,
		asm:    wasm.AI32x4LeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4LeU",
		argLen: 2,
		asm:    wasm.AI32x4LeU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Le",
		argLen: 2,
		asm:    wasm.AF32x4Le,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2LeS",
		argLen: 2,
		asm:    wasm.AI64x2LeS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Le",
		argLen: 2,
		asm:    wasm.AF64x2Le,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Swizzle",
		argLen: 2,
		asm:    wasm.AI8x16Swizzle,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16MaxS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16MaxS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16MaxU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16MaxU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8MaxS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8MaxS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8MaxU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8MaxU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4MaxS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4MaxS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4MaxU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4MaxU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Max",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Max,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Max",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Max,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16MinS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16MinS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16MinU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16MinU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8MinS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8MinS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8MinU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8MinU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4MinS",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4MinS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4MinU",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4MinU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Min",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Min,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Min",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Min,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8Mul",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4Mul",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Mul",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2Mul",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Mul",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Mul,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8ExtmulHighI8x16S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8ExtmulHighI8x16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8ExtmulHighI8x16U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8ExtmulHighI8x16U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4ExtmulHighI16x8S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4ExtmulHighI16x8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4ExtmulHighI16x8U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4ExtmulHighI16x8U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2ExtmulHighI32x4S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2ExtmulHighI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2ExtmulHighI32x4U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2ExtmulHighI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8ExtmulLowI8x16S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8ExtmulLowI8x16S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8ExtmulLowI8x16U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8ExtmulLowI8x16U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4ExtmulLowI16x8S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4ExtmulLowI16x8S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4ExtmulLowI16x8U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4ExtmulLowI16x8U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2ExtmulLowI32x4S",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2ExtmulLowI32x4S,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2ExtmulLowI32x4U",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2ExtmulLowI32x4U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Neg",
		argLen: 1,
		asm:    wasm.AI8x16Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Neg",
		argLen: 1,
		asm:    wasm.AI16x8Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4Neg",
		argLen: 1,
		asm:    wasm.AI32x4Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Neg",
		argLen: 1,
		asm:    wasm.AF32x4Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2Neg",
		argLen: 1,
		asm:    wasm.AI64x2Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Neg",
		argLen: 1,
		asm:    wasm.AF64x2Neg,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "V128Not",
		argLen: 1,
		asm:    wasm.AV128Not,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I8x16Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI8x16Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I16x8Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI16x8Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I32x4Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI32x4Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F32x4Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF32x4Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "I64x2Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AI64x2Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "F64x2Ne",
		argLen:      2,
		commutative: true,
		asm:         wasm.AF64x2Ne,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Popcnt",
		argLen: 1,
		asm:    wasm.AI8x16Popcnt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "V128Or",
		argLen:      2,
		commutative: true,
		asm:         wasm.AV128Or,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Nearest",
		argLen: 1,
		asm:    wasm.AF32x4Nearest,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Nearest",
		argLen: 1,
		asm:    wasm.AF64x2Nearest,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I8x16ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AI8x16ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I16x8ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AI16x8ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I32x4ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AI32x4ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "F32x4ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AF32x4ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 4294901760, v2: 0}},           // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "I64x2ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AI64x2ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:    "F64x2ReplaceLane",
		auxType: auxUInt8,
		argLen:  2,
		asm:     wasm.AF64x2ReplaceLane,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 281470681743360, v2: 0}},      // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Shl",
		argLen: 2,
		asm:    wasm.AI8x16Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Shl",
		argLen: 2,
		asm:    wasm.AI16x8Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4Shl",
		argLen: 2,
		asm:    wasm.AI32x4Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2Shl",
		argLen: 2,
		asm:    wasm.AI64x2Shl,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16ShrS",
		argLen: 2,
		asm:    wasm.AI8x16ShrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16ShrU",
		argLen: 2,
		asm:    wasm.AI8x16ShrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ShrS",
		argLen: 2,
		asm:    wasm.AI16x8ShrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8ShrU",
		argLen: 2,
		asm:    wasm.AI16x8ShrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ShrS",
		argLen: 2,
		asm:    wasm.AI32x4ShrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4ShrU",
		argLen: 2,
		asm:    wasm.AI32x4ShrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ShrS",
		argLen: 2,
		asm:    wasm.AI64x2ShrS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2ShrU",
		argLen: 2,
		asm:    wasm.AI64x2ShrU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 65535, v2: 0}},                // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Sqrt",
		argLen: 1,
		asm:    wasm.AF32x4Sqrt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Sqrt",
		argLen: 1,
		asm:    wasm.AF64x2Sqrt,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16Sub",
		argLen: 2,
		asm:    wasm.AI8x16Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8Sub",
		argLen: 2,
		asm:    wasm.AI16x8Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I32x4Sub",
		argLen: 2,
		asm:    wasm.AI32x4Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Sub",
		argLen: 2,
		asm:    wasm.AF32x4Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I64x2Sub",
		argLen: 2,
		asm:    wasm.AI64x2Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Sub",
		argLen: 2,
		asm:    wasm.AF64x2Sub,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16SubSatS",
		argLen: 2,
		asm:    wasm.AI8x16SubSatS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I8x16SubSatU",
		argLen: 2,
		asm:    wasm.AI8x16SubSatU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8SubSatS",
		argLen: 2,
		asm:    wasm.AI16x8SubSatS,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "I16x8SubSatU",
		argLen: 2,
		asm:    wasm.AI16x8SubSatU,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F32x4Trunc",
		argLen: 1,
		asm:    wasm.AF32x4Trunc,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:   "F64x2Trunc",
		argLen: 1,
		asm:    wasm.AF64x2Trunc,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},
	{
		name:        "V128Xor",
		argLen:      2,
		commutative: true,
		asm:         wasm.AV128Xor,
		reg: regInfo{
			inputs: []inputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
				{1, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
			outputs: []outputInfo{
				{0, regMask{v1: 18446462598732840960, v2: 0}}, // V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15
			},
		},
	},

	{
		name:    "Last",
		argLen:  -1,
		generic: true,
	},
	{
		name:        "Add8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "AddPtr",
		argLen:  2,
		generic: true,
	},
	{
		name:        "Add32F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add64F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Sub8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubPtr",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub64F",
		argLen:  2,
		generic: true,
	},
	{
		name:        "Mul8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul32F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul64F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Div32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div64F",
		argLen:  2,
		generic: true,
	},
	{
		name:        "Hmul32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Hmul32u",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Hmul64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Hmul64u",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul32uhilo",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul64uhilo",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul32uover",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Mul64uover",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Avg32u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Avg64u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div8u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div16u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div32u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div64u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Div128u",
		argLen:  3,
		generic: true,
	},
	{
		name:    "Mod8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod8u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod16u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod32u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Mod64u",
		argLen:  2,
		generic: true,
	},
	{
		name:        "And8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "And16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "And32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "And64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Or8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Or16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Or32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Or64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Xor8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Xor16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Xor32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Xor64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Lsh8x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh8x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh8x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh8x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh16x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh16x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh16x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh16x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh32x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh32x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh32x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh32x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh64x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh64x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh64x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Lsh64x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64x8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64x16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64x32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64x64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8Ux8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8Ux16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8Ux32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh8Ux64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16Ux8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16Ux16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16Ux32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh16Ux64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32Ux8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32Ux16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32Ux32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh32Ux64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64Ux8",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64Ux16",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64Ux32",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:    "Rsh64Ux64",
		auxType: auxBool,
		argLen:  2,
		generic: true,
	},
	{
		name:        "Eq8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Eq16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Eq32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Eq64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqPtr",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "EqInter",
		argLen:  2,
		generic: true,
	},
	{
		name:    "EqSlice",
		argLen:  2,
		generic: true,
	},
	{
		name:        "Eq32F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Eq64F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Neq8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Neq16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Neq32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Neq64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NeqPtr",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "NeqInter",
		argLen:  2,
		generic: true,
	},
	{
		name:    "NeqSlice",
		argLen:  2,
		generic: true,
	},
	{
		name:        "Neq32F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Neq64F",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Less8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less8U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less16U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less32U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less64U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Less64F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq8U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq16U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq32U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq64U",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Leq64F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CondSelect",
		argLen:  3,
		generic: true,
	},
	{
		name:        "AndB",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrB",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqB",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NeqB",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Not",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Neg64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Com8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Com16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Com32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Com64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz64On32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Ctz8NonZero",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz16NonZero",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz32NonZero",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ctz64NonZero",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitLen8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitLen16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitLen32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitLen64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Bswap16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Bswap32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Bswap64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitRev8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitRev16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitRev32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BitRev64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "PopCount8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "PopCount16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "PopCount32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "PopCount64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RotateLeft64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeft32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeft16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeft8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sqrt",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Sqrt32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Floor",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Ceil",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Round",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundToEven",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Abs",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Copysign",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Min64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Max64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Min64u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Max64u",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Min64F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Min32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Max64F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Max32F",
		argLen:  2,
		generic: true,
	},
	{
		name:    "FMA",
		argLen:  3,
		generic: true,
	},
	{
		name:      "Phi",
		argLen:    -1,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:    "Copy",
		argLen:  1,
		generic: true,
	},
	{
		name:         "Convert",
		argLen:       2,
		resultInArg0: true,
		zeroWidth:    true,
		generic:      true,
	},
	{
		name:    "ConstBool",
		auxType: auxBool,
		argLen:  0,
		generic: true,
	},
	{
		name:    "ConstString",
		auxType: auxString,
		argLen:  0,
		generic: true,
	},
	{
		name:    "ConstNil",
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const8",
		auxType: auxInt8,
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const16",
		auxType: auxInt16,
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const32",
		auxType: auxInt32,
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const64",
		auxType: auxInt64,
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const32F",
		auxType: auxFloat32,
		argLen:  0,
		generic: true,
	},
	{
		name:    "Const64F",
		auxType: auxFloat64,
		argLen:  0,
		generic: true,
	},
	{
		name:    "ConstInterface",
		argLen:  0,
		generic: true,
	},
	{
		name:    "ConstSlice",
		argLen:  0,
		generic: true,
	},
	{
		name:      "InitMem",
		argLen:    0,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:      "Arg",
		auxType:   auxSymOff,
		argLen:    0,
		zeroWidth: true,
		symEffect: SymRead,
		generic:   true,
	},
	{
		name:      "ArgIntReg",
		auxType:   auxNameOffsetInt8,
		argLen:    0,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:      "ArgFloatReg",
		auxType:   auxNameOffsetInt8,
		argLen:    0,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:      "Addr",
		auxType:   auxSym,
		argLen:    1,
		symEffect: SymAddr,
		generic:   true,
	},
	{
		name:      "LocalAddr",
		auxType:   auxSym,
		argLen:    2,
		symEffect: SymAddr,
		generic:   true,
	},
	{
		name:      "SP",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		generic:   true,
	},
	{
		name:      "SB",
		argLen:    0,
		zeroWidth: true,
		fixedReg:  true,
		generic:   true,
	},
	{
		name:      "SPanchored",
		argLen:    2,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:    "Load",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Dereference",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Store",
		auxType: auxTyp,
		argLen:  3,
		generic: true,
	},
	{
		name:    "LoadMasked8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "LoadMasked16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "LoadMasked32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "LoadMasked64",
		argLen:  3,
		generic: true,
	},
	{
		name:    "StoreMasked8",
		auxType: auxTyp,
		argLen:  4,
		generic: true,
	},
	{
		name:    "StoreMasked16",
		auxType: auxTyp,
		argLen:  4,
		generic: true,
	},
	{
		name:    "StoreMasked32",
		auxType: auxTyp,
		argLen:  4,
		generic: true,
	},
	{
		name:    "StoreMasked64",
		auxType: auxTyp,
		argLen:  4,
		generic: true,
	},
	{
		name:    "Move",
		auxType: auxTypSize,
		argLen:  3,
		generic: true,
	},
	{
		name:    "Zero",
		auxType: auxTypSize,
		argLen:  2,
		generic: true,
	},
	{
		name:    "StoreWB",
		auxType: auxTyp,
		argLen:  3,
		generic: true,
	},
	{
		name:    "MoveWB",
		auxType: auxTypSize,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ZeroWB",
		auxType: auxTypSize,
		argLen:  2,
		generic: true,
	},
	{
		name:    "WBend",
		argLen:  1,
		generic: true,
	},
	{
		name:    "WB",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:      "HasCPUFeature",
		auxType:   auxSym,
		argLen:    0,
		symEffect: SymNone,
		generic:   true,
	},
	{
		name:    "PanicBounds",
		auxType: auxInt64,
		argLen:  3,
		call:    true,
		generic: true,
	},
	{
		name:    "PanicExtend",
		auxType: auxInt64,
		argLen:  4,
		call:    true,
		generic: true,
	},
	{
		name:    "ClosureCall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "StaticCall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "InterCall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "TailCall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "TailCallInter",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "ClosureLECall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "StaticLECall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "InterLECall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "TailLECall",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "TailLECallInter",
		auxType: auxCallOff,
		argLen:  -1,
		call:    true,
		generic: true,
	},
	{
		name:    "SignExt8to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SignExt8to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SignExt8to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SignExt16to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SignExt16to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SignExt32to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt8to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt8to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt8to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt16to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt16to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ZeroExt32to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc16to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc32to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc32to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc64to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc64to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Trunc64to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32to32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32to64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64to32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64to64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Fto32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Fto64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Fto32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Fto64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Fto64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Fto32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtBoolToUint8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Round32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Round64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNonNil",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsInBounds",
		argLen:  2,
		generic: true,
	},
	{
		name:    "IsSliceInBounds",
		argLen:  2,
		generic: true,
	},
	{
		name:     "NilCheck",
		argLen:   2,
		nilCheck: true,
		generic:  true,
	},
	{
		name:      "GetG",
		argLen:    1,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:    "GetClosurePtr",
		argLen:  0,
		generic: true,
	},
	{
		name:    "GetCallerPC",
		argLen:  0,
		generic: true,
	},
	{
		name:    "GetCallerSP",
		argLen:  1,
		generic: true,
	},
	{
		name:    "PtrIndex",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OffPtr",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:    "SliceMake",
		argLen:  3,
		generic: true,
	},
	{
		name:    "SlicePtr",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SliceLen",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SliceCap",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SlicePtrUnchecked",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ComplexMake",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ComplexReal",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ComplexImag",
		argLen:  1,
		generic: true,
	},
	{
		name:    "StringMake",
		argLen:  2,
		generic: true,
	},
	{
		name:    "StringPtr",
		argLen:  1,
		generic: true,
	},
	{
		name:    "StringLen",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IMake",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ITab",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IData",
		argLen:  1,
		generic: true,
	},
	{
		name:    "StructMake",
		argLen:  -1,
		generic: true,
	},
	{
		name:    "StructSelect",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:    "ArrayMake1",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ArraySelect",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:    "StoreReg",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LoadReg",
		argLen:  1,
		generic: true,
	},
	{
		name:      "FwdRef",
		auxType:   auxSym,
		argLen:    0,
		symEffect: SymNone,
		generic:   true,
	},
	{
		name:    "Unknown",
		argLen:  0,
		generic: true,
	},
	{
		name:      "VarDef",
		auxType:   auxSym,
		argLen:    1,
		zeroWidth: true,
		symEffect: SymNone,
		generic:   true,
	},
	{
		name:      "VarLive",
		auxType:   auxSym,
		argLen:    1,
		zeroWidth: true,
		symEffect: SymRead,
		generic:   true,
	},
	{
		name:      "KeepAlive",
		argLen:    2,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:    "InlMark",
		auxType: auxInt32,
		argLen:  1,
		generic: true,
	},
	{
		name:    "Int64Make",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Int64Hi",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Int64Lo",
		argLen:  1,
		generic: true,
	},
	{
		name:        "Add32carry",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add32withcarry",
		argLen:      3,
		commutative: true,
		generic:     true,
	},
	{
		name:        "Add32carrywithcarry",
		argLen:      3,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Sub32carry",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Sub32withcarry",
		argLen:  3,
		generic: true,
	},
	{
		name:        "Add64carry",
		argLen:      3,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Sub64borrow",
		argLen:  3,
		generic: true,
	},
	{
		name:    "Signmask",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Zeromask",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Slicemask",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SpectreIndex",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SpectreSliceIndex",
		argLen:  2,
		generic: true,
	},
	{
		name:    "Cvt32Uto32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Uto64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Fto32U",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Fto32U",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Uto32F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Uto64F",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32Fto64U",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64Fto64U",
		argLen:  1,
		generic: true,
	},
	{
		name:      "Select0",
		argLen:    1,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:      "Select1",
		argLen:    1,
		zeroWidth: true,
		generic:   true,
	},
	{
		name:    "MakeTuple",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SelectN",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:    "SelectNAddr",
		auxType: auxInt64,
		argLen:  1,
		generic: true,
	},
	{
		name:    "MakeResult",
		argLen:  -1,
		generic: true,
	},
	{
		name:    "AtomicLoad8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AtomicLoad32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AtomicLoad64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AtomicLoadPtr",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AtomicLoadAcq32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AtomicLoadAcq64",
		argLen:  2,
		generic: true,
	},
	{
		name:           "AtomicStore8",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStore32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStore64",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStorePtrNoWB",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStoreRel32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStoreRel64",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange8",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange64",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAdd32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAdd64",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicCompareAndSwap32",
		argLen:         4,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicCompareAndSwap64",
		argLen:         4,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicCompareAndSwapRel32",
		argLen:         4,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd8",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr8",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr32",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd64value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd32value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd8value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr64value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr32value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr8value",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStore8Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStore32Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicStore64Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAdd32Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAdd64Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange8Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange32Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicExchange64Variant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicCompareAndSwap32Variant",
		argLen:         4,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicCompareAndSwap64Variant",
		argLen:         4,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd64valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr64valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd32valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr32valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicAnd8valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "AtomicOr8valueVariant",
		argLen:         3,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "PubBarrier",
		argLen:         1,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:      "Clobber",
		auxType:   auxSymOff,
		argLen:    0,
		symEffect: SymNone,
		generic:   true,
	},
	{
		name:    "ClobberReg",
		argLen:  0,
		generic: true,
	},
	{
		name:           "PrefetchCache",
		argLen:         2,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:           "PrefetchCacheStreamed",
		argLen:         2,
		hasSideEffects: true,
		generic:        true,
	},
	{
		name:        "MemEq",
		argLen:      4,
		commutative: true,
		generic:     true,
	},
	{
		name:    "Empty",
		argLen:  0,
		generic: true,
	},
	{
		name:    "ZeroSIMD",
		argLen:  0,
		generic: true,
	},
	{
		name:    "Cvt16toMask8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32toMask8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt64toMask8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt16toMask16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt32toMask16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt16toMask32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "Cvt8toMask64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask8x16to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask8x32to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask8x64to64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask16x8to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask16x16to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask16x32to32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask32x4to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask32x8to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask32x16to16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask64x2to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask64x4to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CvtMask64x8to8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsZeroVec",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "IsNaNFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AESDecryptLastRoundUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESDecryptLastRoundUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESDecryptLastRoundUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESDecryptOneRoundUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESDecryptOneRoundUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESDecryptOneRoundUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptLastRoundUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptLastRoundUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptLastRoundUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptOneRoundUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptOneRoundUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESEncryptOneRoundUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AESInvMixColumnsUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AbsInt64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:        "AddFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "AddOddSubEvenFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AddOddSubEvenFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AddOddSubEvenFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AddOddSubEvenFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:        "AddSaturatedInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddSaturatedUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AddUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "AndNotInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "AndNotUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:        "AndUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AndUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "AverageUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "BitSelectInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectInt16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectInt32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectInt64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectUint8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectUint16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectUint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BitSelectUint64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "BroadcastFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BroadcastFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BroadcastInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BroadcastInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BroadcastInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "BroadcastInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "CompressFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "CompressUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsGroupedUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsSaturatedGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsSaturatedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatAddPairsUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatEvenUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatOddUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteFloat64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt8x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt8x64",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteInt64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint8x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint8x64",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatPermuteUint64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ConcatSubPairsFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsGroupedUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsSaturatedGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsSaturatedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatSubPairsUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConvertLo2ToFloat64Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertLo2ToFloat64Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertLo2ToFloat64Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Float64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Float64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat32Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Float32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToFloat64Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt32Float64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt64Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt64Float32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt64Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt64Float64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToInt64Float64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint32Float64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint64Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint64Float32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint64Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint64Float64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConvertToUint64Float64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "DivFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DivFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DivFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DivFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DivFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DivFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsSaturatedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsSaturatedUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "DotProductPairsSaturatedUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:        "EqualFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "EqualUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "ExpandFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExpandUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ExtendHi2ToInt64Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendHi2ToUint64Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendHi4ToInt32Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendHi4ToUint32Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendHi8ToInt16Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendHi8ToUint16Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToInt64Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToInt64Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToInt64Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToUint64Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToUint64Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo2ToUint64Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToInt32Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToInt32Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToInt64Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToInt64Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToUint32Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToUint32Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToUint64Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo4ToUint64Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToInt16Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToInt32Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToInt64Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToUint16Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToUint32Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendLo8ToUint64Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt16Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt16Int8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt32Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt32Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt32Int16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt64Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt64Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToInt64Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint16Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint16Uint8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint32Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint32Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint32Uint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint64Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint64Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ExtendToUint64Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GaloisFieldMulUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldMulUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldMulUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GetHiFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiInt64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetHiUint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoInt64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetLoUint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterEqualUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "GreaterUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveEvenUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiGroupedUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveHiUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoGroupedUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveLoUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "InterleaveOddUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LeadingSignBitsInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingSignBitsInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingSignBitsInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingSignBitsUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingSignBitsUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingSignBitsUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosInt64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LeadingZerosUint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "LessEqualFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessEqualUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LessUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LookupOrZeroInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "LookupOrZeroUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:        "MaxFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MaxUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MinUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "MulAddEvenSubOddFloat32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddEvenSubOddFloat32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddEvenSubOddFloat32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddEvenSubOddFloat64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddEvenSubOddFloat64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddEvenSubOddFloat64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddFloat64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddInt16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddInt32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddOddSubEvenFloat64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddUint8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddUint16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "MulAddUint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:        "MulFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulHighUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "MulSignInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "MulSignInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "MulSignInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "MulSignInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "MulSignInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "MulSignInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:        "MulUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenEvenInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenEvenInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenEvenUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenEvenUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenHiUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "MulWidenLoUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "NegFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NegFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NegInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NegInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NegInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NegInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:        "NotEqualFloat32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualFloat32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualFloat32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualFloat64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualFloat64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualFloat64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "NotEqualUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "NotInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "NotUint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountInt64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint8x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint8x64",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "OnesCountUint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:        "OrInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "OrNotInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "OrNotUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:        "OrUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "OrUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "PermuteFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroGroupedInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroGroupedInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroGroupedUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroGroupedUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteOrZeroUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "PermuteUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ReciprocalFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ReciprocalSqrtFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllLeftVarUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateAllRightVarUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateLeftUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RotateRightUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "RoundFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SHA1Message1Uint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SHA1Message2Uint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SHA1NextEUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SHA256Message1Uint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SHA256Message2Uint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SHA256TwoRoundsUint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt8Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16ConcatGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToInt16ConcatGroupedInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToInt16ConcatInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt16Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt32Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt32Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToInt32Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint8Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16ConcatGroupedInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToUint16ConcatGroupedInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToUint16ConcatInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SaturateToUint16Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint16Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint32Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint32Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint32Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SaturateToUint32Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "ScaleFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ScaleFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ScaleFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ScaleFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ScaleFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ScaleFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetHiUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetLoUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Int16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Int16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Int16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Uint16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Uint16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod16Uint16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Int32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Int32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Int32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Uint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Uint32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod32Uint32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Int64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Int64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Int64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Uint64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Uint64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftConcatMod64Uint64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftLeftInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftLeftUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Int16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Int16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Int16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Uint16x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Uint16x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod16Uint16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Int32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Int32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Int32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Uint32x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Uint32x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod32Uint32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Int64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Int64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Int64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Uint64x2",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Uint64x4",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightConcatMod64Uint64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "ShiftRightInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftRightUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftSaturatedUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SqrtFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SqrtFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SqrtFloat32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SqrtFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SqrtFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SqrtFloat64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "SubFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubFloat32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubFloat32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubFloat64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubFloat64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubInt64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubSaturatedUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint16x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint16x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint32x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint32x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint64x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SubUint64x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SumOf8AbsDiffUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SumOf8AbsDiffUint8x32",
		argLen:  2,
		generic: true,
	},
	{
		name:    "SumOf8AbsDiffUint8x64",
		argLen:  2,
		generic: true,
	},
	{
		name:    "TruncFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncFloat32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncFloat64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncFloat64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt8Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt16Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt32Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt32Int64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToInt32Int64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint16x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint16x32",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint8Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint32x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint32x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint16Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint32Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint32Uint64x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncToUint32Uint64x8",
		argLen:  1,
		generic: true,
	},
	{
		name:        "XorInt8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorInt64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint8x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint8x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint8x64",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint16x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint16x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint16x32",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint32x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint32x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint32x16",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint64x4",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:        "XorUint64x8",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "bitSelectInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "bitSelectNotInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendInt8x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendInt8x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendMaskedInt8x64",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendMaskedInt16x32",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendMaskedInt32x16",
		argLen:  3,
		generic: true,
	},
	{
		name:    "blendMaskedInt64x8",
		argLen:  3,
		generic: true,
	},
	{
		name:    "broadcast1To2Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To2Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To2MaskedFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To2MaskedInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To2MaskedUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To2Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4MaskedUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To4Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To4Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Float64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Int64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedFloat64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedInt64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8MaskedUint64x2",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To8Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To8Uint64x2",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Float32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Int32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedFloat32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedInt32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16MaskedUint32x4",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To16Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To16Uint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To32Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To32Int16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To32MaskedInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To32MaskedInt16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To32MaskedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To32MaskedUint16x8",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To32Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To32Uint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To64Int8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "broadcast1To64MaskedInt8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To64MaskedUint8x16",
		argLen:  2,
		generic: true,
	},
	{
		name:    "broadcast1To64Uint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:        "carrylessMultiplyWidenLoUint64x2",
		argLen:      2,
		commutative: true,
		generic:     true,
	},
	{
		name:    "reduceMaxFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMaxUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinFloat32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceMinUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumInt8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumInt16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumInt32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumUint8x16",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumUint16x8",
		argLen:  1,
		generic: true,
	},
	{
		name:    "reduceSumUint32x4",
		argLen:  1,
		generic: true,
	},
	{
		name:    "AESRoundKeyGenAssistUint32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "CeilScaledResidueFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsFloat32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsFloat64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsInt8x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsInt16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsInt32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsInt64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsUint8x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsUint16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsUint32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatPermute128ScalarsUint64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatShiftBytesRightGroupedUint8x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatShiftBytesRightGroupedUint8x64",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ConcatShiftBytesRightUint8x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "FloorScaledFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "FloorScaledResidueFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformInverseUint8x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformInverseUint8x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformInverseUint8x64",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformUint8x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformUint8x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GaloisFieldAffineTransformUint8x64",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "GetElemFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemInt8x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemInt16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemInt32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemInt64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemUint8x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemUint16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemUint32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "GetElemUint64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "RoundScaledResidueFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "SHA1FourRoundsUint32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemFloat32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemFloat64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemInt8x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemInt16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemInt32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemInt64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemUint8x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemUint16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemUint32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "SetElemUint64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Int16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Int16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Int16x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Uint16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Uint16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod16Uint16x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Int32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Int32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Int32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Uint32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Uint32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod32Uint32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Int64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Int64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Int64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Uint64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Uint64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllLeftConcatMod64Uint64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Int16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Int16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Int16x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Uint16x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Uint16x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod16Uint16x32",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Int32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Int32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Int32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Uint32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Uint32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod32Uint32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Int64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Int64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Int64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Uint64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Uint64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "ShiftAllRightConcatMod64Uint64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "TruncScaledFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat64x2",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat64x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "TruncScaledResidueFloat64x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "carrylessMultiplyUint64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "carrylessMultiplyUint64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "carrylessMultiplyUint64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantFloat32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantFloat64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedFloat32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedFloat32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedFloat64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedFloat64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedInt32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedInt32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedInt64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedInt64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedUint32x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedUint32x16",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedUint64x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantGroupedUint64x8",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantInt32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantInt64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantUint32x4",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "concatSelectedConstantUint64x2",
		auxType: auxUInt8,
		argLen:  2,
		generic: true,
	},
	{
		name:    "permuteScalarsGroupedInt32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsGroupedInt32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsGroupedUint32x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsGroupedUint32x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiGroupedInt16x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiGroupedInt16x32",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiGroupedUint16x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiGroupedUint16x32",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiInt16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsHiUint16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsInt32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoGroupedInt16x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoGroupedInt16x32",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoGroupedUint16x16",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoGroupedUint16x32",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoInt16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsLoUint16x8",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "permuteScalarsUint32x4",
		auxType: auxUInt8,
		argLen:  1,
		generic: true,
	},
	{
		name:    "ternInt32x4",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternInt32x8",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternInt32x16",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternInt64x2",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternInt64x4",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternInt64x8",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint32x4",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint32x8",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint32x16",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint64x2",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint64x4",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
	{
		name:    "ternUint64x8",
		auxType: auxUInt8,
		argLen:  3,
		generic: true,
	},
}

func (o Op) Asm() obj.As          { return opcodeTable[o].asm }
func (o Op) Scale() int16         { return int16(opcodeTable[o].scale) }
func (o Op) String() string       { return opcodeTable[o].name }
func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect }
func (o Op) IsCall() bool         { return opcodeTable[o].call }
func (o Op) IsTailCall() bool     { return opcodeTable[o].tailCall }
func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects }
func (o Op) UnsafePoint() bool    { return opcodeTable[o].unsafePoint }
func (o Op) ResultInArg0() bool   { return opcodeTable[o].resultInArg0 }

var registers386 = [...]Register{
	{0, x86.REG_AX, "AX"},
	{1, x86.REG_CX, "CX"},
	{2, x86.REG_DX, "DX"},
	{3, x86.REG_BX, "BX"},
	{4, x86.REGSP, "SP"},
	{5, x86.REG_BP, "BP"},
	{6, x86.REG_SI, "SI"},
	{7, x86.REG_DI, "DI"},
	{8, x86.REG_X0, "X0"},
	{9, x86.REG_X1, "X1"},
	{10, x86.REG_X2, "X2"},
	{11, x86.REG_X3, "X3"},
	{12, x86.REG_X4, "X4"},
	{13, x86.REG_X5, "X5"},
	{14, x86.REG_X6, "X6"},
	{15, x86.REG_X7, "X7"},
	{16, 0, "SB"},
}
var paramIntReg386 = []int8(nil)
var paramFloatReg386 = []int8(nil)
var gpRegMask386 = regMask{v1: 239, v2: 0}
var fpRegMask386 = regMask{v1: 65280, v2: 0}
var specialRegMask386 = regMask{v1: 0, v2: 0}
var framepointerReg386 = int8(5)
var linkReg386 = int8(-1)
var registersAMD64 = [...]Register{
	{0, x86.REG_AX, "AX"},
	{1, x86.REG_CX, "CX"},
	{2, x86.REG_DX, "DX"},
	{3, x86.REG_BX, "BX"},
	{4, x86.REGSP, "SP"},
	{5, x86.REG_BP, "BP"},
	{6, x86.REG_SI, "SI"},
	{7, x86.REG_DI, "DI"},
	{8, x86.REG_R8, "R8"},
	{9, x86.REG_R9, "R9"},
	{10, x86.REG_R10, "R10"},
	{11, x86.REG_R11, "R11"},
	{12, x86.REG_R12, "R12"},
	{13, x86.REG_R13, "R13"},
	{14, x86.REGG, "g"},
	{15, x86.REG_R15, "R15"},
	{16, x86.REG_X0, "X0"},
	{17, x86.REG_X1, "X1"},
	{18, x86.REG_X2, "X2"},
	{19, x86.REG_X3, "X3"},
	{20, x86.REG_X4, "X4"},
	{21, x86.REG_X5, "X5"},
	{22, x86.REG_X6, "X6"},
	{23, x86.REG_X7, "X7"},
	{24, x86.REG_X8, "X8"},
	{25, x86.REG_X9, "X9"},
	{26, x86.REG_X10, "X10"},
	{27, x86.REG_X11, "X11"},
	{28, x86.REG_X12, "X12"},
	{29, x86.REG_X13, "X13"},
	{30, x86.REG_X14, "X14"},
	{31, x86.REG_X15, "X15"},
	{32, x86.REG_X16, "X16"},
	{33, x86.REG_X17, "X17"},
	{34, x86.REG_X18, "X18"},
	{35, x86.REG_X19, "X19"},
	{36, x86.REG_X20, "X20"},
	{37, x86.REG_X21, "X21"},
	{38, x86.REG_X22, "X22"},
	{39, x86.REG_X23, "X23"},
	{40, x86.REG_X24, "X24"},
	{41, x86.REG_X25, "X25"},
	{42, x86.REG_X26, "X26"},
	{43, x86.REG_X27, "X27"},
	{44, x86.REG_X28, "X28"},
	{45, x86.REG_X29, "X29"},
	{46, x86.REG_X30, "X30"},
	{47, x86.REG_X31, "X31"},
	{48, x86.REG_K0, "K0"},
	{49, x86.REG_K1, "K1"},
	{50, x86.REG_K2, "K2"},
	{51, x86.REG_K3, "K3"},
	{52, x86.REG_K4, "K4"},
	{53, x86.REG_K5, "K5"},
	{54, x86.REG_K6, "K6"},
	{55, x86.REG_K7, "K7"},
	{56, 0, "SB"},
}
var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
var gpRegMaskAMD64 = regMask{v1: 49135, v2: 0}
var fpRegMaskAMD64 = regMask{v1: 2147418112, v2: 0}
var simdRegMaskAMD64 = regMask{v1: 2147418112, v2: 0}
var specialRegMaskAMD64 = regMask{v1: 71776114766249984, v2: 0}
var framepointerRegAMD64 = int8(5)
var linkRegAMD64 = int8(-1)
var registersARM = [...]Register{
	{0, arm.REG_R0, "R0"},
	{1, arm.REG_R1, "R1"},
	{2, arm.REG_R2, "R2"},
	{3, arm.REG_R3, "R3"},
	{4, arm.REG_R4, "R4"},
	{5, arm.REG_R5, "R5"},
	{6, arm.REG_R6, "R6"},
	{7, arm.REG_R7, "R7"},
	{8, arm.REG_R8, "R8"},
	{9, arm.REG_R9, "R9"},
	{10, arm.REGG, "g"},
	{11, arm.REG_R11, "R11"},
	{12, arm.REG_R12, "R12"},
	{13, arm.REGSP, "SP"},
	{14, arm.REG_R14, "R14"},
	{15, arm.REG_R15, "R15"},
	{16, arm.REG_F0, "F0"},
	{17, arm.REG_F1, "F1"},
	{18, arm.REG_F2, "F2"},
	{19, arm.REG_F3, "F3"},
	{20, arm.REG_F4, "F4"},
	{21, arm.REG_F5, "F5"},
	{22, arm.REG_F6, "F6"},
	{23, arm.REG_F7, "F7"},
	{24, arm.REG_F8, "F8"},
	{25, arm.REG_F9, "F9"},
	{26, arm.REG_F10, "F10"},
	{27, arm.REG_F11, "F11"},
	{28, arm.REG_F12, "F12"},
	{29, arm.REG_F13, "F13"},
	{30, arm.REG_F14, "F14"},
	{31, arm.REG_F15, "F15"},
	{32, 0, "SB"},
}
var paramIntRegARM = []int8(nil)
var paramFloatRegARM = []int8(nil)
var gpRegMaskARM = regMask{v1: 21503, v2: 0}
var fpRegMaskARM = regMask{v1: 4294901760, v2: 0}
var specialRegMaskARM = regMask{v1: 0, v2: 0}
var framepointerRegARM = int8(-1)
var linkRegARM = int8(14)
var registersARM64 = [...]Register{
	{0, arm64.REG_R0, "R0"},
	{1, arm64.REG_R1, "R1"},
	{2, arm64.REG_R2, "R2"},
	{3, arm64.REG_R3, "R3"},
	{4, arm64.REG_R4, "R4"},
	{5, arm64.REG_R5, "R5"},
	{6, arm64.REG_R6, "R6"},
	{7, arm64.REG_R7, "R7"},
	{8, arm64.REG_R8, "R8"},
	{9, arm64.REG_R9, "R9"},
	{10, arm64.REG_R10, "R10"},
	{11, arm64.REG_R11, "R11"},
	{12, arm64.REG_R12, "R12"},
	{13, arm64.REG_R13, "R13"},
	{14, arm64.REG_R14, "R14"},
	{15, arm64.REG_R15, "R15"},
	{16, arm64.REG_R16, "R16"},
	{17, arm64.REG_R17, "R17"},
	{18, arm64.REG_R19, "R19"},
	{19, arm64.REG_R20, "R20"},
	{20, arm64.REG_R21, "R21"},
	{21, arm64.REG_R22, "R22"},
	{22, arm64.REG_R23, "R23"},
	{23, arm64.REG_R24, "R24"},
	{24, arm64.REG_R25, "R25"},
	{25, arm64.REG_R26, "R26"},
	{26, arm64.REGG, "g"},
	{27, arm64.REG_R29, "R29"},
	{28, arm64.REG_R30, "R30"},
	{29, arm64.REGZERO, "ZERO"},
	{30, arm64.REGSP, "SP"},
	{31, arm64.REG_F0, "F0"},
	{32, arm64.REG_F1, "F1"},
	{33, arm64.REG_F2, "F2"},
	{34, arm64.REG_F3, "F3"},
	{35, arm64.REG_F4, "F4"},
	{36, arm64.REG_F5, "F5"},
	{37, arm64.REG_F6, "F6"},
	{38, arm64.REG_F7, "F7"},
	{39, arm64.REG_F8, "F8"},
	{40, arm64.REG_F9, "F9"},
	{41, arm64.REG_F10, "F10"},
	{42, arm64.REG_F11, "F11"},
	{43, arm64.REG_F12, "F12"},
	{44, arm64.REG_F13, "F13"},
	{45, arm64.REG_F14, "F14"},
	{46, arm64.REG_F15, "F15"},
	{47, arm64.REG_F16, "F16"},
	{48, arm64.REG_F17, "F17"},
	{49, arm64.REG_F18, "F18"},
	{50, arm64.REG_F19, "F19"},
	{51, arm64.REG_F20, "F20"},
	{52, arm64.REG_F21, "F21"},
	{53, arm64.REG_F22, "F22"},
	{54, arm64.REG_F23, "F23"},
	{55, arm64.REG_F24, "F24"},
	{56, arm64.REG_F25, "F25"},
	{57, arm64.REG_F26, "F26"},
	{58, arm64.REG_F27, "F27"},
	{59, arm64.REG_F28, "F28"},
	{60, arm64.REG_F29, "F29"},
	{61, arm64.REG_F30, "F30"},
	{62, arm64.REG_F31, "F31"},
	{63, 0, "SB"},
}
var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46}
var gpRegMaskARM64 = regMask{v1: 335544319, v2: 0}
var fpRegMaskARM64 = regMask{v1: 9223372034707292160, v2: 0}
var simdRegMaskARM64 = regMask{v1: 9223372034707292160, v2: 0}
var specialRegMaskARM64 = regMask{v1: 0, v2: 0}
var framepointerRegARM64 = int8(-1)
var linkRegARM64 = int8(28)
var registersLOONG64 = [...]Register{
	{0, loong64.REGZERO, "ZERO"},
	{1, loong64.REG_R1, "R1"},
	{2, loong64.REGSP, "SP"},
	{3, loong64.REG_R4, "R4"},
	{4, loong64.REG_R5, "R5"},
	{5, loong64.REG_R6, "R6"},
	{6, loong64.REG_R7, "R7"},
	{7, loong64.REG_R8, "R8"},
	{8, loong64.REG_R9, "R9"},
	{9, loong64.REG_R10, "R10"},
	{10, loong64.REG_R11, "R11"},
	{11, loong64.REG_R12, "R12"},
	{12, loong64.REG_R13, "R13"},
	{13, loong64.REG_R14, "R14"},
	{14, loong64.REG_R15, "R15"},
	{15, loong64.REG_R16, "R16"},
	{16, loong64.REG_R17, "R17"},
	{17, loong64.REG_R18, "R18"},
	{18, loong64.REG_R19, "R19"},
	{19, loong64.REG_R20, "R20"},
	{20, loong64.REG_R21, "R21"},
	{21, loong64.REGG, "g"},
	{22, loong64.REG_R23, "R23"},
	{23, loong64.REG_R24, "R24"},
	{24, loong64.REG_R25, "R25"},
	{25, loong64.REG_R26, "R26"},
	{26, loong64.REG_R27, "R27"},
	{27, loong64.REG_R28, "R28"},
	{28, loong64.REG_R29, "R29"},
	{29, loong64.REG_R31, "R31"},
	{30, loong64.REG_F0, "F0"},
	{31, loong64.REG_F1, "F1"},
	{32, loong64.REG_F2, "F2"},
	{33, loong64.REG_F3, "F3"},
	{34, loong64.REG_F4, "F4"},
	{35, loong64.REG_F5, "F5"},
	{36, loong64.REG_F6, "F6"},
	{37, loong64.REG_F7, "F7"},
	{38, loong64.REG_F8, "F8"},
	{39, loong64.REG_F9, "F9"},
	{40, loong64.REG_F10, "F10"},
	{41, loong64.REG_F11, "F11"},
	{42, loong64.REG_F12, "F12"},
	{43, loong64.REG_F13, "F13"},
	{44, loong64.REG_F14, "F14"},
	{45, loong64.REG_F15, "F15"},
	{46, loong64.REG_F16, "F16"},
	{47, loong64.REG_F17, "F17"},
	{48, loong64.REG_F18, "F18"},
	{49, loong64.REG_F19, "F19"},
	{50, loong64.REG_F20, "F20"},
	{51, loong64.REG_F21, "F21"},
	{52, loong64.REG_F22, "F22"},
	{53, loong64.REG_F23, "F23"},
	{54, loong64.REG_F24, "F24"},
	{55, loong64.REG_F25, "F25"},
	{56, loong64.REG_F26, "F26"},
	{57, loong64.REG_F27, "F27"},
	{58, loong64.REG_F28, "F28"},
	{59, loong64.REG_F29, "F29"},
	{60, loong64.REG_F30, "F30"},
	{61, loong64.REG_F31, "F31"},
	{62, 0, "SB"},
}
var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18}
var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45}
var gpRegMaskLOONG64 = regMask{v1: 1071644664, v2: 0}
var fpRegMaskLOONG64 = regMask{v1: 4611686017353646080, v2: 0}
var specialRegMaskLOONG64 = regMask{v1: 0, v2: 0}
var framepointerRegLOONG64 = int8(-1)
var linkRegLOONG64 = int8(1)
var registersMIPS = [...]Register{
	{0, mips.REG_R0, "R0"},
	{1, mips.REG_R1, "R1"},
	{2, mips.REG_R2, "R2"},
	{3, mips.REG_R3, "R3"},
	{4, mips.REG_R4, "R4"},
	{5, mips.REG_R5, "R5"},
	{6, mips.REG_R6, "R6"},
	{7, mips.REG_R7, "R7"},
	{8, mips.REG_R8, "R8"},
	{9, mips.REG_R9, "R9"},
	{10, mips.REG_R10, "R10"},
	{11, mips.REG_R11, "R11"},
	{12, mips.REG_R12, "R12"},
	{13, mips.REG_R13, "R13"},
	{14, mips.REG_R14, "R14"},
	{15, mips.REG_R15, "R15"},
	{16, mips.REG_R16, "R16"},
	{17, mips.REG_R17, "R17"},
	{18, mips.REG_R18, "R18"},
	{19, mips.REG_R19, "R19"},
	{20, mips.REG_R20, "R20"},
	{21, mips.REG_R21, "R21"},
	{22, mips.REG_R22, "R22"},
	{23, mips.REG_R24, "R24"},
	{24, mips.REG_R25, "R25"},
	{25, mips.REG_R28, "R28"},
	{26, mips.REGSP, "SP"},
	{27, mips.REGG, "g"},
	{28, mips.REG_R31, "R31"},
	{29, mips.REG_F0, "F0"},
	{30, mips.REG_F2, "F2"},
	{31, mips.REG_F4, "F4"},
	{32, mips.REG_F6, "F6"},
	{33, mips.REG_F8, "F8"},
	{34, mips.REG_F10, "F10"},
	{35, mips.REG_F12, "F12"},
	{36, mips.REG_F14, "F14"},
	{37, mips.REG_F16, "F16"},
	{38, mips.REG_F18, "F18"},
	{39, mips.REG_F20, "F20"},
	{40, mips.REG_F22, "F22"},
	{41, mips.REG_F24, "F24"},
	{42, mips.REG_F26, "F26"},
	{43, mips.REG_F28, "F28"},
	{44, mips.REG_F30, "F30"},
	{45, mips.REG_HI, "HI"},
	{46, mips.REG_LO, "LO"},
	{47, 0, "SB"},
}
var paramIntRegMIPS = []int8(nil)
var paramFloatRegMIPS = []int8(nil)
var gpRegMaskMIPS = regMask{v1: 335544318, v2: 0}
var fpRegMaskMIPS = regMask{v1: 35183835217920, v2: 0}
var specialRegMaskMIPS = regMask{v1: 105553116266496, v2: 0}
var framepointerRegMIPS = int8(-1)
var linkRegMIPS = int8(28)
var registersMIPS64 = [...]Register{
	{0, mips.REGZERO, "ZERO"},
	{1, mips.REG_R1, "R1"},
	{2, mips.REG_R2, "R2"},
	{3, mips.REG_R3, "R3"},
	{4, mips.REG_R4, "R4"},
	{5, mips.REG_R5, "R5"},
	{6, mips.REG_R6, "R6"},
	{7, mips.REG_R7, "R7"},
	{8, mips.REG_R8, "R8"},
	{9, mips.REG_R9, "R9"},
	{10, mips.REG_R10, "R10"},
	{11, mips.REG_R11, "R11"},
	{12, mips.REG_R12, "R12"},
	{13, mips.REG_R13, "R13"},
	{14, mips.REG_R14, "R14"},
	{15, mips.REG_R15, "R15"},
	{16, mips.REG_R16, "R16"},
	{17, mips.REG_R17, "R17"},
	{18, mips.REG_R18, "R18"},
	{19, mips.REG_R19, "R19"},
	{20, mips.REG_R20, "R20"},
	{21, mips.REG_R21, "R21"},
	{22, mips.REG_R22, "R22"},
	{23, mips.REG_R24, "R24"},
	{24, mips.REG_R25, "R25"},
	{25, mips.REGSP, "SP"},
	{26, mips.REGG, "g"},
	{27, mips.REG_R31, "R31"},
	{28, mips.REG_F0, "F0"},
	{29, mips.REG_F1, "F1"},
	{30, mips.REG_F2, "F2"},
	{31, mips.REG_F3, "F3"},
	{32, mips.REG_F4, "F4"},
	{33, mips.REG_F5, "F5"},
	{34, mips.REG_F6, "F6"},
	{35, mips.REG_F7, "F7"},
	{36, mips.REG_F8, "F8"},
	{37, mips.REG_F9, "F9"},
	{38, mips.REG_F10, "F10"},
	{39, mips.REG_F11, "F11"},
	{40, mips.REG_F12, "F12"},
	{41, mips.REG_F13, "F13"},
	{42, mips.REG_F14, "F14"},
	{43, mips.REG_F15, "F15"},
	{44, mips.REG_F16, "F16"},
	{45, mips.REG_F17, "F17"},
	{46, mips.REG_F18, "F18"},
	{47, mips.REG_F19, "F19"},
	{48, mips.REG_F20, "F20"},
	{49, mips.REG_F21, "F21"},
	{50, mips.REG_F22, "F22"},
	{51, mips.REG_F23, "F23"},
	{52, mips.REG_F24, "F24"},
	{53, mips.REG_F25, "F25"},
	{54, mips.REG_F26, "F26"},
	{55, mips.REG_F27, "F27"},
	{56, mips.REG_F28, "F28"},
	{57, mips.REG_F29, "F29"},
	{58, mips.REG_F30, "F30"},
	{59, mips.REG_F31, "F31"},
	{60, mips.REG_HI, "HI"},
	{61, mips.REG_LO, "LO"},
	{62, 0, "SB"},
}
var paramIntRegMIPS64 = []int8(nil)
var paramFloatRegMIPS64 = []int8(nil)
var gpRegMaskMIPS64 = regMask{v1: 167772158, v2: 0}
var fpRegMaskMIPS64 = regMask{v1: 1152921504338411520, v2: 0}
var specialRegMaskMIPS64 = regMask{v1: 3458764513820540928, v2: 0}
var framepointerRegMIPS64 = int8(-1)
var linkRegMIPS64 = int8(27)
var registersPPC64 = [...]Register{
	{0, ppc64.REG_R0, "R0"},
	{1, ppc64.REGSP, "SP"},
	{2, 0, "SB"},
	{3, ppc64.REG_R3, "R3"},
	{4, ppc64.REG_R4, "R4"},
	{5, ppc64.REG_R5, "R5"},
	{6, ppc64.REG_R6, "R6"},
	{7, ppc64.REG_R7, "R7"},
	{8, ppc64.REG_R8, "R8"},
	{9, ppc64.REG_R9, "R9"},
	{10, ppc64.REG_R10, "R10"},
	{11, ppc64.REG_R11, "R11"},
	{12, ppc64.REG_R12, "R12"},
	{13, ppc64.REG_R13, "R13"},
	{14, ppc64.REG_R14, "R14"},
	{15, ppc64.REG_R15, "R15"},
	{16, ppc64.REG_R16, "R16"},
	{17, ppc64.REG_R17, "R17"},
	{18, ppc64.REG_R18, "R18"},
	{19, ppc64.REG_R19, "R19"},
	{20, ppc64.REG_R20, "R20"},
	{21, ppc64.REG_R21, "R21"},
	{22, ppc64.REG_R22, "R22"},
	{23, ppc64.REG_R23, "R23"},
	{24, ppc64.REG_R24, "R24"},
	{25, ppc64.REG_R25, "R25"},
	{26, ppc64.REG_R26, "R26"},
	{27, ppc64.REG_R27, "R27"},
	{28, ppc64.REG_R28, "R28"},
	{29, ppc64.REG_R29, "R29"},
	{30, ppc64.REGG, "g"},
	{31, ppc64.REG_R31, "R31"},
	{32, ppc64.REG_F0, "F0"},
	{33, ppc64.REG_F1, "F1"},
	{34, ppc64.REG_F2, "F2"},
	{35, ppc64.REG_F3, "F3"},
	{36, ppc64.REG_F4, "F4"},
	{37, ppc64.REG_F5, "F5"},
	{38, ppc64.REG_F6, "F6"},
	{39, ppc64.REG_F7, "F7"},
	{40, ppc64.REG_F8, "F8"},
	{41, ppc64.REG_F9, "F9"},
	{42, ppc64.REG_F10, "F10"},
	{43, ppc64.REG_F11, "F11"},
	{44, ppc64.REG_F12, "F12"},
	{45, ppc64.REG_F13, "F13"},
	{46, ppc64.REG_F14, "F14"},
	{47, ppc64.REG_F15, "F15"},
	{48, ppc64.REG_F16, "F16"},
	{49, ppc64.REG_F17, "F17"},
	{50, ppc64.REG_F18, "F18"},
	{51, ppc64.REG_F19, "F19"},
	{52, ppc64.REG_F20, "F20"},
	{53, ppc64.REG_F21, "F21"},
	{54, ppc64.REG_F22, "F22"},
	{55, ppc64.REG_F23, "F23"},
	{56, ppc64.REG_F24, "F24"},
	{57, ppc64.REG_F25, "F25"},
	{58, ppc64.REG_F26, "F26"},
	{59, ppc64.REG_F27, "F27"},
	{60, ppc64.REG_F28, "F28"},
	{61, ppc64.REG_F29, "F29"},
	{62, ppc64.REG_F30, "F30"},
	{63, ppc64.REG_XER, "XER"},
}
var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17}
var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44}
var gpRegMaskPPC64 = regMask{v1: 1073733624, v2: 0}
var fpRegMaskPPC64 = regMask{v1: 9223372032559808512, v2: 0}
var specialRegMaskPPC64 = regMask{v1: 9223372036854775808, v2: 0}
var framepointerRegPPC64 = int8(-1)
var linkRegPPC64 = int8(-1)
var registersRISCV64 = [...]Register{
	{0, riscv.REG_X0, "X0"},
	{1, riscv.REGSP, "SP"},
	{2, riscv.REG_X3, "X3"},
	{3, riscv.REG_X4, "X4"},
	{4, riscv.REG_X5, "X5"},
	{5, riscv.REG_X6, "X6"},
	{6, riscv.REG_X7, "X7"},
	{7, riscv.REG_X8, "X8"},
	{8, riscv.REG_X9, "X9"},
	{9, riscv.REG_X10, "X10"},
	{10, riscv.REG_X11, "X11"},
	{11, riscv.REG_X12, "X12"},
	{12, riscv.REG_X13, "X13"},
	{13, riscv.REG_X14, "X14"},
	{14, riscv.REG_X15, "X15"},
	{15, riscv.REG_X16, "X16"},
	{16, riscv.REG_X17, "X17"},
	{17, riscv.REG_X18, "X18"},
	{18, riscv.REG_X19, "X19"},
	{19, riscv.REG_X20, "X20"},
	{20, riscv.REG_X21, "X21"},
	{21, riscv.REG_X22, "X22"},
	{22, riscv.REG_X23, "X23"},
	{23, riscv.REG_X24, "X24"},
	{24, riscv.REG_X25, "X25"},
	{25, riscv.REG_X26, "X26"},
	{26, riscv.REGG, "g"},
	{27, riscv.REG_X28, "X28"},
	{28, riscv.REG_X29, "X29"},
	{29, riscv.REG_X30, "X30"},
	{30, riscv.REG_X31, "X31"},
	{31, riscv.REG_F0, "F0"},
	{32, riscv.REG_F1, "F1"},
	{33, riscv.REG_F2, "F2"},
	{34, riscv.REG_F3, "F3"},
	{35, riscv.REG_F4, "F4"},
	{36, riscv.REG_F5, "F5"},
	{37, riscv.REG_F6, "F6"},
	{38, riscv.REG_F7, "F7"},
	{39, riscv.REG_F8, "F8"},
	{40, riscv.REG_F9, "F9"},
	{41, riscv.REG_F10, "F10"},
	{42, riscv.REG_F11, "F11"},
	{43, riscv.REG_F12, "F12"},
	{44, riscv.REG_F13, "F13"},
	{45, riscv.REG_F14, "F14"},
	{46, riscv.REG_F15, "F15"},
	{47, riscv.REG_F16, "F16"},
	{48, riscv.REG_F17, "F17"},
	{49, riscv.REG_F18, "F18"},
	{50, riscv.REG_F19, "F19"},
	{51, riscv.REG_F20, "F20"},
	{52, riscv.REG_F21, "F21"},
	{53, riscv.REG_F22, "F22"},
	{54, riscv.REG_F23, "F23"},
	{55, riscv.REG_F24, "F24"},
	{56, riscv.REG_F25, "F25"},
	{57, riscv.REG_F26, "F26"},
	{58, riscv.REG_F27, "F27"},
	{59, riscv.REG_F28, "F28"},
	{60, riscv.REG_F29, "F29"},
	{61, riscv.REG_F30, "F30"},
	{62, riscv.REG_F31, "F31"},
	{63, 0, "SB"},
}
var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22}
var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54}
var gpRegMaskRISCV64 = regMask{v1: 1006632944, v2: 0}
var fpRegMaskRISCV64 = regMask{v1: 9223372034707292160, v2: 0}
var specialRegMaskRISCV64 = regMask{v1: 0, v2: 0}
var framepointerRegRISCV64 = int8(-1)
var linkRegRISCV64 = int8(0)
var registersS390X = [...]Register{
	{0, s390x.REG_R0, "R0"},
	{1, s390x.REG_R1, "R1"},
	{2, s390x.REG_R2, "R2"},
	{3, s390x.REG_R3, "R3"},
	{4, s390x.REG_R4, "R4"},
	{5, s390x.REG_R5, "R5"},
	{6, s390x.REG_R6, "R6"},
	{7, s390x.REG_R7, "R7"},
	{8, s390x.REG_R8, "R8"},
	{9, s390x.REG_R9, "R9"},
	{10, s390x.REG_R10, "R10"},
	{11, s390x.REG_R11, "R11"},
	{12, s390x.REG_R12, "R12"},
	{13, s390x.REGG, "g"},
	{14, s390x.REG_R14, "R14"},
	{15, s390x.REGSP, "SP"},
	{16, s390x.REG_F0, "F0"},
	{17, s390x.REG_F1, "F1"},
	{18, s390x.REG_F2, "F2"},
	{19, s390x.REG_F3, "F3"},
	{20, s390x.REG_F4, "F4"},
	{21, s390x.REG_F5, "F5"},
	{22, s390x.REG_F6, "F6"},
	{23, s390x.REG_F7, "F7"},
	{24, s390x.REG_F8, "F8"},
	{25, s390x.REG_F9, "F9"},
	{26, s390x.REG_F10, "F10"},
	{27, s390x.REG_F11, "F11"},
	{28, s390x.REG_F12, "F12"},
	{29, s390x.REG_F13, "F13"},
	{30, s390x.REG_F14, "F14"},
	{31, s390x.REG_F15, "F15"},
	{32, 0, "SB"},
}
var paramIntRegS390X = []int8{2, 3, 4, 5, 6, 7, 8, 9}
var paramFloatRegS390X = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}
var gpRegMaskS390X = regMask{v1: 23551, v2: 0}
var fpRegMaskS390X = regMask{v1: 4294901760, v2: 0}
var specialRegMaskS390X = regMask{v1: 0, v2: 0}
var framepointerRegS390X = int8(-1)
var linkRegS390X = int8(14)
var registersWasm = [...]Register{
	{0, wasm.REG_R0, "R0"},
	{1, wasm.REG_R1, "R1"},
	{2, wasm.REG_R2, "R2"},
	{3, wasm.REG_R3, "R3"},
	{4, wasm.REG_R4, "R4"},
	{5, wasm.REG_R5, "R5"},
	{6, wasm.REG_R6, "R6"},
	{7, wasm.REG_R7, "R7"},
	{8, wasm.REG_R8, "R8"},
	{9, wasm.REG_R9, "R9"},
	{10, wasm.REG_R10, "R10"},
	{11, wasm.REG_R11, "R11"},
	{12, wasm.REG_R12, "R12"},
	{13, wasm.REG_R13, "R13"},
	{14, wasm.REG_R14, "R14"},
	{15, wasm.REG_R15, "R15"},
	{16, wasm.REG_F0, "F0"},
	{17, wasm.REG_F1, "F1"},
	{18, wasm.REG_F2, "F2"},
	{19, wasm.REG_F3, "F3"},
	{20, wasm.REG_F4, "F4"},
	{21, wasm.REG_F5, "F5"},
	{22, wasm.REG_F6, "F6"},
	{23, wasm.REG_F7, "F7"},
	{24, wasm.REG_F8, "F8"},
	{25, wasm.REG_F9, "F9"},
	{26, wasm.REG_F10, "F10"},
	{27, wasm.REG_F11, "F11"},
	{28, wasm.REG_F12, "F12"},
	{29, wasm.REG_F13, "F13"},
	{30, wasm.REG_F14, "F14"},
	{31, wasm.REG_F15, "F15"},
	{32, wasm.REG_F16, "F16"},
	{33, wasm.REG_F17, "F17"},
	{34, wasm.REG_F18, "F18"},
	{35, wasm.REG_F19, "F19"},
	{36, wasm.REG_F20, "F20"},
	{37, wasm.REG_F21, "F21"},
	{38, wasm.REG_F22, "F22"},
	{39, wasm.REG_F23, "F23"},
	{40, wasm.REG_F24, "F24"},
	{41, wasm.REG_F25, "F25"},
	{42, wasm.REG_F26, "F26"},
	{43, wasm.REG_F27, "F27"},
	{44, wasm.REG_F28, "F28"},
	{45, wasm.REG_F29, "F29"},
	{46, wasm.REG_F30, "F30"},
	{47, wasm.REG_F31, "F31"},
	{48, wasm.REG_V0, "V0"},
	{49, wasm.REG_V1, "V1"},
	{50, wasm.REG_V2, "V2"},
	{51, wasm.REG_V3, "V3"},
	{52, wasm.REG_V4, "V4"},
	{53, wasm.REG_V5, "V5"},
	{54, wasm.REG_V6, "V6"},
	{55, wasm.REG_V7, "V7"},
	{56, wasm.REG_V8, "V8"},
	{57, wasm.REG_V9, "V9"},
	{58, wasm.REG_V10, "V10"},
	{59, wasm.REG_V11, "V11"},
	{60, wasm.REG_V12, "V12"},
	{61, wasm.REG_V13, "V13"},
	{62, wasm.REG_V14, "V14"},
	{63, wasm.REG_V15, "V15"},
	{64, wasm.REGSP, "SP"},
	{65, wasm.REGG, "g"},
	{66, 0, "SB"},
}
var paramIntRegWasm = []int8(nil)
var paramFloatRegWasm = []int8(nil)
var gpRegMaskWasm = regMask{v1: 65535, v2: 0}
var fpRegMaskWasm = regMask{v1: 281474976645120, v2: 0}
var fp32RegMaskWasm = regMask{v1: 4294901760, v2: 0}
var fp64RegMaskWasm = regMask{v1: 281470681743360, v2: 0}
var simdRegMaskWasm = regMask{v1: 18446462598732840960, v2: 0}
var specialRegMaskWasm = regMask{v1: 0, v2: 0}
var framepointerRegWasm = int8(-1)
var linkRegWasm = int8(-1)
